xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs404.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QCS404 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <mani@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,pcie-qcs404
17
18  reg:
19    maxItems: 4
20
21  reg-names:
22    items:
23      - const: dbi
24      - const: elbi
25      - const: parf
26      - const: config
27
28  clocks:
29    maxItems: 4
30
31  clock-names:
32    items:
33      - const: iface # AHB clock
34      - const: aux
35      - const: master_bus # AXI Master clock
36      - const: slave_bus # AXI Slave clock
37
38  interrupts:
39    maxItems: 1
40
41  interrupt-names:
42    items:
43      - const: msi
44
45  resets:
46    maxItems: 6
47
48  reset-names:
49    items:
50      - const: axi_m # AXI Master reset
51      - const: axi_s # AXI Slave reset
52      - const: axi_m_sticky # AXI Master Sticky reset
53      - const: pipe_sticky
54      - const: pwr
55      - const: ahb
56
57required:
58  - resets
59  - reset-names
60
61allOf:
62  - $ref: qcom,pcie-common.yaml#
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
69    #include <dt-bindings/gpio/gpio.h>
70    #include <dt-bindings/interrupt-controller/arm-gic.h>
71
72    pcie@10000000 {
73        compatible = "qcom,pcie-qcs404";
74        reg = <0x10000000 0xf1d>,
75              <0x10000f20 0xa8>,
76              <0x07780000 0x2000>,
77              <0x10001000 0x2000>;
78        reg-names = "dbi", "elbi", "parf", "config";
79        ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
80                 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
81
82        device_type = "pci";
83        linux,pci-domain = <0>;
84        bus-range = <0x00 0xff>;
85        num-lanes = <1>;
86        #address-cells = <3>;
87        #size-cells = <2>;
88
89        clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
90                 <&gcc GCC_PCIE_0_AUX_CLK>,
91                 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
92                 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
93        clock-names = "iface", "aux", "master_bus", "slave_bus";
94
95        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
96        interrupt-names = "msi";
97        #interrupt-cells = <1>;
98        interrupt-map-mask = <0 0 0 0x7>;
99        interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
100                        <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
101                        <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
102                        <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
103
104        phys = <&pcie_phy>;
105        phy-names = "pciephy";
106
107        perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
108
109        resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
110                 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
111                 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
112                 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
113                 <&gcc GCC_PCIE_0_BCR>,
114                 <&gcc GCC_PCIE_0_AHB_ARES>;
115        reset-names = "axi_m",
116                      "axi_s",
117                      "axi_m_sticky",
118                      "pipe_sticky",
119                      "pwr",
120                      "ahb";
121
122        pcie@0 {
123            device_type = "pci";
124            reg = <0x0 0x0 0x0 0x0 0x0>;
125            bus-range = <0x01 0xff>;
126
127            #address-cells = <3>;
128            #size-cells = <2>;
129            ranges;
130        };
131    };
132