xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-ipq8074.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq8074.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ8074 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <mani@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,pcie-ipq8074
17
18  reg:
19    maxItems: 4
20
21  reg-names:
22    items:
23      - const: dbi
24      - const: elbi
25      - const: parf
26      - const: config
27
28  clocks:
29    maxItems: 5
30
31  clock-names:
32    items:
33      - const: iface # PCIe to SysNOC BIU clock
34      - const: axi_m # AXI Master clock
35      - const: axi_s # AXI Slave clock
36      - const: ahb
37      - const: aux
38
39  interrupts:
40    maxItems: 9
41
42  interrupt-names:
43    items:
44      - const: msi0
45      - const: msi1
46      - const: msi2
47      - const: msi3
48      - const: msi4
49      - const: msi5
50      - const: msi6
51      - const: msi7
52      - const: global
53
54  resets:
55    maxItems: 7
56
57  reset-names:
58    items:
59      - const: pipe
60      - const: sleep
61      - const: sticky # Core sticky reset
62      - const: axi_m # AXI master reset
63      - const: axi_s # AXI slave reset
64      - const: ahb
65      - const: axi_m_sticky # AXI master sticky reset
66
67required:
68  - resets
69  - reset-names
70
71allOf:
72  - $ref: qcom,pcie-common.yaml#
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
79    #include <dt-bindings/gpio/gpio.h>
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81
82    pcie@10000000 {
83        compatible = "qcom,pcie-ipq8074";
84        reg = <0x10000000 0xf1d>,
85              <0x10000f20 0xa8>,
86              <0x00088000 0x2000>,
87              <0x10100000 0x1000>;
88        reg-names = "dbi", "elbi", "parf", "config";
89        ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
90                 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
91
92        device_type = "pci";
93        linux,pci-domain = <1>;
94        bus-range = <0x00 0xff>;
95        num-lanes = <1>;
96        max-link-speed = <2>;
97        #address-cells = <3>;
98        #size-cells = <2>;
99
100        clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
101                 <&gcc GCC_PCIE1_AXI_M_CLK>,
102                 <&gcc GCC_PCIE1_AXI_S_CLK>,
103                 <&gcc GCC_PCIE1_AHB_CLK>,
104                 <&gcc GCC_PCIE1_AUX_CLK>;
105        clock-names = "iface",
106                      "axi_m",
107                      "axi_s",
108                      "ahb",
109                      "aux";
110
111        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
113                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
114                     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
115                     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
116                     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
117                     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
118                     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
119                     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
120        interrupt-names = "msi0",
121                          "msi1",
122                          "msi2",
123                          "msi3",
124                          "msi4",
125                          "msi5",
126                          "msi6",
127                          "msi7",
128                          "global";
129        #interrupt-cells = <1>;
130        interrupt-map-mask = <0 0 0 0x7>;
131        interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
132                        <0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
133                        <0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
134                        <0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
135
136        phys = <&pcie_qmp1>;
137        phy-names = "pciephy";
138
139        resets = <&gcc GCC_PCIE1_PIPE_ARES>,
140                 <&gcc GCC_PCIE1_SLEEP_ARES>,
141                 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
142                 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
143                 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
144                 <&gcc GCC_PCIE1_AHB_ARES>,
145                 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
146        reset-names = "pipe",
147                      "sleep",
148                      "sticky",
149                      "axi_m",
150                      "axi_s",
151                      "ahb",
152                      "axi_m_sticky";
153
154        perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
155
156        pcie@0 {
157            device_type = "pci";
158            reg = <0x0 0x0 0x0 0x0 0x0>;
159            bus-range = <0x01 0xff>;
160
161            #address-cells = <3>;
162            #size-cells = <2>;
163            ranges;
164        };
165    };
166