xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq6018.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ6018 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <mani@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,pcie-ipq6018
17      - qcom,pcie-ipq8074-gen3
18
19  reg:
20    minItems: 5
21    maxItems: 6
22
23  reg-names:
24    minItems: 5
25    items:
26      - const: dbi
27      - const: elbi
28      - const: atu
29      - const: parf
30      - const: config
31      - const: mhi
32
33  clocks:
34    maxItems: 5
35
36  clock-names:
37    items:
38      - const: iface # PCIe to SysNOC BIU clock
39      - const: axi_m # AXI Master clock
40      - const: axi_s # AXI Slave clock
41      - const: axi_bridge
42      - const: rchng
43
44  interrupts:
45    maxItems: 9
46
47  interrupt-names:
48    items:
49      - const: msi0
50      - const: msi1
51      - const: msi2
52      - const: msi3
53      - const: msi4
54      - const: msi5
55      - const: msi6
56      - const: msi7
57      - const: global
58
59  resets:
60    maxItems: 8
61
62  reset-names:
63    items:
64      - const: pipe
65      - const: sleep
66      - const: sticky # Core sticky reset
67      - const: axi_m # AXI master reset
68      - const: axi_s # AXI slave reset
69      - const: ahb
70      - const: axi_m_sticky # AXI master sticky reset
71      - const: axi_s_sticky # AXI slave sticky reset
72
73required:
74  - resets
75  - reset-names
76
77allOf:
78  - $ref: qcom,pcie-common.yaml#
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
85    #include <dt-bindings/gpio/gpio.h>
86    #include <dt-bindings/interrupt-controller/arm-gic.h>
87    #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
88
89    soc {
90        #address-cells = <2>;
91        #size-cells = <2>;
92
93        pcie@20000000 {
94            compatible = "qcom,pcie-ipq6018";
95            reg = <0x0 0x20000000 0x0 0xf1d>,
96                  <0x0 0x20000f20 0x0 0xa8>,
97                  <0x0 0x20001000 0x0 0x1000>,
98                  <0x0 0x80000 0x0 0x4000>,
99                  <0x0 0x20100000 0x0 0x1000>;
100            reg-names = "dbi", "elbi", "atu", "parf", "config";
101            ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
102                     <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
103
104            device_type = "pci";
105            linux,pci-domain = <0>;
106            bus-range = <0x00 0xff>;
107            num-lanes = <1>;
108            max-link-speed = <3>;
109            #address-cells = <3>;
110            #size-cells = <2>;
111
112            clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
113                     <&gcc GCC_PCIE0_AXI_M_CLK>,
114                     <&gcc GCC_PCIE0_AXI_S_CLK>,
115                     <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
116                     <&gcc PCIE0_RCHNG_CLK>;
117            clock-names = "iface",
118                          "axi_m",
119                          "axi_s",
120                          "axi_bridge",
121                          "rchng";
122
123            interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
124                         <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
125                         <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
126                         <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
127                         <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
128                         <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
129                         <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
130                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
131                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
132            interrupt-names = "msi0",
133                              "msi1",
134                              "msi2",
135                              "msi3",
136                              "msi4",
137                              "msi5",
138                              "msi6",
139                              "msi7",
140                              "global";
141
142            #interrupt-cells = <1>;
143            interrupt-map-mask = <0 0 0 0x7>;
144            interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
145                            <0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
146                            <0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
147                            <0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
148
149            phys = <&pcie_phy>;
150            phy-names = "pciephy";
151
152            resets = <&gcc GCC_PCIE0_PIPE_ARES>,
153                     <&gcc GCC_PCIE0_SLEEP_ARES>,
154                     <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
155                     <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
156                     <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
157                     <&gcc GCC_PCIE0_AHB_ARES>,
158                     <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
159                     <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
160            reset-names = "pipe",
161                          "sleep",
162                          "sticky",
163                          "axi_m",
164                          "axi_s",
165                          "ahb",
166                          "axi_m_sticky",
167                          "axi_s_sticky";
168
169            pcie@0 {
170                device_type = "pci";
171                reg = <0x0 0x0 0x0 0x0 0x0>;
172                bus-range = <0x01 0xff>;
173
174                #address-cells = <3>;
175                #size-cells = <2>;
176                ranges;
177            };
178        };
179    };
180