xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm APQ8084 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <mani@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,pcie-apq8084
17
18  reg:
19    minItems: 4
20    maxItems: 5
21
22  reg-names:
23    minItems: 4
24    items:
25      - const: parf
26      - const: dbi
27      - const: elbi
28      - const: config
29      - const: mhi
30
31  clocks:
32    maxItems: 4
33
34  clock-names:
35    items:
36      - const: iface # Configuration AHB clock
37      - const: master_bus # Master AXI clock
38      - const: slave_bus # Slave AXI clock
39      - const: aux
40
41  interrupts:
42    maxItems: 1
43
44  interrupt-names:
45    items:
46      - const: msi
47
48  resets:
49    maxItems: 1
50
51  reset-names:
52    items:
53      - const: core
54
55  vdda-supply:
56    description: A phandle to the core analog power supply
57
58required:
59  - power-domains
60  - resets
61  - reset-names
62
63allOf:
64  - $ref: qcom,pcie-common.yaml#
65
66unevaluatedProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/interrupt-controller/arm-gic.h>
71    #include <dt-bindings/gpio/gpio.h>
72    pcie@fc520000 {
73      compatible = "qcom,pcie-apq8084";
74      reg = <0xfc520000 0x2000>,
75            <0xff000000 0x1000>,
76            <0xff001000 0x1000>,
77            <0xff002000 0x2000>;
78      reg-names = "parf", "dbi", "elbi", "config";
79      device_type = "pci";
80      linux,pci-domain = <0>;
81      bus-range = <0x00 0xff>;
82      num-lanes = <1>;
83      #address-cells = <3>;
84      #size-cells = <2>;
85      ranges = <0x81000000 0 0          0xff200000 0 0x00100000>,
86               <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
87      interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
88      interrupt-names = "msi";
89      #interrupt-cells = <1>;
90      interrupt-map-mask = <0 0 0 0x7>;
91      interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
92                      <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
93                      <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
94                      <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
95      clocks = <&gcc 324>,
96               <&gcc 325>,
97               <&gcc 327>,
98               <&gcc 323>;
99      clock-names = "iface", "master_bus", "slave_bus", "aux";
100      resets = <&gcc 81>;
101      reset-names = "core";
102      power-domains = <&gcc 1>;
103      vdda-supply = <&pma8084_l3>;
104      phys = <&pciephy0>;
105      phy-names = "pciephy";
106      perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
107      pinctrl-0 = <&pcie0_pins_default>;
108      pinctrl-names = "default";
109    };
110