xref: /linux/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml (revision 84318277d6334c6981ab326d4acc87c6a6ddc9b8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller
8
9maintainers:
10  - Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
11  - Ionut Vicovan <ionut.vicovan@nxp.com>
12
13description:
14  This PCIe controller is based on the Synopsys DesignWare PCIe IP.
15  The S32G SoC family has two PCIe controllers, which can be configured as
16  either Root Complex or Endpoint.
17
18properties:
19  compatible:
20    oneOf:
21      - enum:
22          - nxp,s32g2-pcie
23      - items:
24          - const: nxp,s32g3-pcie
25          - const: nxp,s32g2-pcie
26
27  reg:
28    maxItems: 6
29
30  reg-names:
31    items:
32      - const: dbi
33      - const: dbi2
34      - const: atu
35      - const: dma
36      - const: ctrl
37      - const: config
38
39  interrupts:
40    minItems: 1
41    maxItems: 2
42
43  interrupt-names:
44    items:
45      - const: msi
46      - const: dma
47    minItems: 1
48
49  pcie@0:
50    description:
51      Describe the S32G Root Port.
52    type: object
53    $ref: /schemas/pci/pci-pci-bridge.yaml#
54
55    properties:
56      reg:
57        maxItems: 1
58
59      phys:
60        maxItems: 1
61
62    required:
63      - reg
64      - phys
65
66    unevaluatedProperties: false
67
68required:
69  - compatible
70  - reg
71  - reg-names
72  - interrupts
73  - interrupt-names
74  - ranges
75  - pcie@0
76
77allOf:
78  - $ref: /schemas/pci/snps,dw-pcie.yaml#
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/interrupt-controller/arm-gic.h>
85    #include <dt-bindings/phy/phy.h>
86
87    bus {
88        #address-cells = <2>;
89        #size-cells = <2>;
90
91        pcie@40400000 {
92            compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";
93            reg = <0x00 0x40400000 0x0 0x00001000>,   /* dbi registers */
94                  <0x00 0x40420000 0x0 0x00001000>,   /* dbi2 registers */
95                  <0x00 0x40460000 0x0 0x00001000>,   /* atu registers */
96                  <0x00 0x40470000 0x0 0x00001000>,   /* dma registers */
97                  <0x00 0x40481000 0x0 0x000000f8>,   /* ctrl registers */
98                  <0x5f 0xffffe000 0x0 0x00002000>;   /* config space */
99            reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config";
100            dma-coherent;
101            #address-cells = <3>;
102            #size-cells = <2>;
103            device_type = "pci";
104            ranges =
105                     <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
106                     <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,
107                     <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;
108
109            bus-range = <0x0 0xff>;
110            interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
111                         <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
112            interrupt-names = "msi", "dma";
113            #interrupt-cells = <1>;
114            interrupt-map-mask = <0 0 0 0x7>;
115            interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
116                            <0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
117                            <0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
118                            <0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
119
120            pcie@0 {
121                reg = <0x0 0x0 0x0 0x0 0x0>;
122                #address-cells = <3>;
123                #size-cells = <2>;
124                ranges;
125
126                device_type = "pci";
127                phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
128            };
129        };
130    };
131