xref: /linux/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml (revision e65f4718a577fcc84d40431f022985898b6dbf2e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra264 PCIe controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  compatible:
15    const: nvidia,tegra264-pcie
16
17  reg:
18    description: |
19      Of the six PCIe controllers found on Tegra264, one (C0) is used for the
20      internal GPU and the other five (C1-C5) are routed to connectors such as
21      PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
22      through C5, but not for C0.
23    minItems: 4
24    items:
25      - description: ECAM-compatible configuration space
26      - description: application layer registers
27      - description: transaction layer registers
28      - description: privileged transaction layer registers
29      - description: data link/physical layer registers (not available on C0)
30
31  reg-names:
32    minItems: 4
33    items:
34      - const: ecam
35      - const: xal
36      - const: xtl
37      - const: xtl-pri
38      - const: xpl
39
40  interrupts:
41    minItems: 1
42    maxItems: 4
43
44  dma-coherent: true
45
46  nvidia,bpmp:
47    $ref: /schemas/types.yaml#/definitions/phandle-array
48    description: |
49      Must contain a pair of phandle (to the BPMP controller node) and
50      controller ID. The following are the controller IDs for each controller:
51
52      0: C0
53      1: C1
54      2: C2
55      3: C3
56      4: C4
57      5: C5
58    items:
59      - items:
60          - description: phandle to the BPMP controller node
61          - description: PCIe controller ID
62            maximum: 5
63
64required:
65  - interrupt-map
66  - interrupt-map-mask
67  - iommu-map
68  - msi-map
69  - nvidia,bpmp
70
71allOf:
72  - $ref: /schemas/pci/pci-host-bridge.yaml#
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    bus {
79      #address-cells = <2>;
80      #size-cells = <2>;
81
82      pci@c000000 {
83        compatible = "nvidia,tegra264-pcie";
84        reg = <0xd0 0xb0000000 0x0 0x10000000>,
85              <0x00 0x0c000000 0x0 0x00004000>,
86              <0x00 0x0c004000 0x0 0x00001000>,
87              <0x00 0x0c005000 0x0 0x00001000>;
88        reg-names = "ecam", "xal", "xtl", "xtl-pri";
89        #address-cells = <3>;
90        #size-cells = <2>;
91        device_type = "pci";
92        linux,pci-domain = <0x00>;
93        #interrupt-cells = <0x1>;
94
95        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
96        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>,
97                        <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>,
98                        <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>,
99                        <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>;
100
101        iommu-map = <0x0 &smmu2 0x10000 0x10000>;
102        msi-map = <0x0 &its 0x210000 0x10000>;
103        dma-coherent;
104
105        ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>,
106                 <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>,
107                 <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>;
108        bus-range = <0x0 0xff>;
109
110        nvidia,bpmp = <&bpmp 0>;
111      };
112    };
113
114  - |
115    bus {
116      #address-cells = <2>;
117      #size-cells = <2>;
118
119      pci@8400000 {
120        compatible = "nvidia,tegra264-pcie";
121        reg = <0xa8 0xb0000000 0x0 0x10000000>,
122              <0x00 0x08400000 0x0 0x00004000>,
123              <0x00 0x08404000 0x0 0x00001000>,
124              <0x00 0x08405000 0x0 0x00001000>,
125              <0x00 0x08410000 0x0 0x00010000>;
126        reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
127        #address-cells = <3>;
128        #size-cells = <2>;
129        device_type = "pci";
130        linux,pci-domain = <0x01>;
131        #interrupt-cells = <1>;
132        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
133        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>,
134                        <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>,
135                        <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>,
136                        <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>;
137
138        iommu-map = <0x0 &smmu1 0x10000 0x10000>;
139        msi-map = <0x0 &its 0x110000 0x10000>;
140        dma-coherent;
141
142        ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>,
143                 <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>,
144                 <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>;
145        bus-range = <0x00 0xff>;
146
147        nvidia,bpmp = <&bpmp 1>;
148      };
149    };
150