1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: PCIe controller on MediaTek SoCs 8 9maintainers: 10 - Christian Marangi <ansuelsmth@gmail.com> 11 12properties: 13 compatible: 14 oneOf: 15 - enum: 16 - airoha,an7583-pcie 17 - mediatek,mt2712-pcie 18 - mediatek,mt7622-pcie 19 - mediatek,mt7629-pcie 20 - items: 21 - const: airoha,en7523-pcie 22 - const: mediatek,mt7622-pcie 23 24 reg: 25 maxItems: 1 26 27 reg-names: 28 enum: [ port0, port1 ] 29 30 clocks: 31 minItems: 1 32 maxItems: 6 33 34 clock-names: 35 minItems: 1 36 items: 37 - enum: [ sys_ck0, sys_ck1 ] 38 - enum: [ ahb_ck0, ahb_ck1 ] 39 - enum: [ aux_ck0, aux_ck1 ] 40 - enum: [ axi_ck0, axi_ck1 ] 41 - enum: [ obff_ck0, obff_ck1 ] 42 - enum: [ pipe_ck0, pipe_ck1 ] 43 44 resets: 45 maxItems: 1 46 47 reset-names: 48 const: pcie-rst1 49 50 interrupts: 51 maxItems: 1 52 53 interrupt-names: 54 const: pcie_irq 55 56 phys: 57 maxItems: 1 58 59 phy-names: 60 enum: [ pcie-phy0, pcie-phy1 ] 61 62 power-domains: 63 maxItems: 1 64 65 mediatek,pbus-csr: 66 $ref: /schemas/types.yaml#/definitions/phandle-array 67 items: 68 - items: 69 - description: phandle to pbus-csr syscon 70 - description: offset of pbus-csr base address register 71 - description: offset of pbus-csr base address mask register 72 description: 73 Phandle with two arguments to the syscon node used to detect if 74 a given address is accessible on PCIe controller. 75 76 '#interrupt-cells': 77 const: 1 78 79 interrupt-controller: 80 description: Interrupt controller node for handling legacy PCI interrupts. 81 type: object 82 properties: 83 '#address-cells': 84 const: 0 85 '#interrupt-cells': 86 const: 1 87 interrupt-controller: true 88 89 required: 90 - '#address-cells' 91 - '#interrupt-cells' 92 - interrupt-controller 93 94 additionalProperties: false 95 96required: 97 - compatible 98 - reg 99 - reg-names 100 - ranges 101 - clocks 102 - clock-names 103 - '#interrupt-cells' 104 - interrupts 105 - interrupt-names 106 - interrupt-controller 107 108allOf: 109 - $ref: /schemas/pci/pci-host-bridge.yaml# 110 111 - if: 112 properties: 113 compatible: 114 const: airoha,an7583-pcie 115 then: 116 properties: 117 reg-names: 118 const: port1 119 120 clocks: 121 maxItems: 1 122 123 clock-names: 124 const: sys_ck1 125 126 phy-names: 127 const: pcie-phy1 128 129 power-domain: false 130 131 required: 132 - resets 133 - reset-names 134 - phys 135 - phy-names 136 - mediatek,pbus-csr 137 138 - if: 139 properties: 140 compatible: 141 const: mediatek,mt2712-pcie 142 then: 143 properties: 144 clocks: 145 minItems: 2 146 maxItems: 2 147 148 clock-names: 149 minItems: 2 150 maxItems: 2 151 152 reset: false 153 154 reset-names: false 155 156 power-domains: false 157 158 mediatek,pbus-csr: false 159 160 required: 161 - phys 162 - phy-names 163 164 - if: 165 properties: 166 compatible: 167 const: mediatek,mt7622-pcie 168 then: 169 properties: 170 clocks: 171 minItems: 6 172 173 reset: false 174 175 reset-names: false 176 177 phys: false 178 179 phy-names: false 180 181 mediatek,pbus-csr: false 182 183 required: 184 - power-domains 185 186 - if: 187 properties: 188 compatible: 189 const: mediatek,mt7629-pcie 190 then: 191 properties: 192 clocks: 193 minItems: 6 194 195 reset: false 196 197 reset-names: false 198 199 mediatek,pbus-csr: false 200 201 required: 202 - power-domains 203 204 - if: 205 properties: 206 compatible: 207 contains: 208 const: airoha,en7523-pcie 209 then: 210 properties: 211 clocks: 212 maxItems: 1 213 214 clock-names: 215 maxItems: 1 216 217 reset: false 218 219 reset-names: false 220 221 phys: false 222 223 phy-names: false 224 225 power-domain: false 226 227 mediatek,pbus-csr: false 228 229unevaluatedProperties: false 230 231examples: 232 # MT2712 233 - | 234 #include <dt-bindings/interrupt-controller/arm-gic.h> 235 #include <dt-bindings/interrupt-controller/irq.h> 236 #include <dt-bindings/phy/phy.h> 237 238 soc_1 { 239 #address-cells = <2>; 240 #size-cells = <2>; 241 242 pcie@112ff000 { 243 compatible = "mediatek,mt2712-pcie"; 244 device_type = "pci"; 245 reg = <0 0x112ff000 0 0x1000>; 246 reg-names = "port1"; 247 linux,pci-domain = <1>; 248 #address-cells = <3>; 249 #size-cells = <2>; 250 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 251 interrupt-names = "pcie_irq"; 252 clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ 253 <&pericfg>; /* CLK_PERI_PCIE1 */ 254 clock-names = "sys_ck1", "ahb_ck1"; 255 phys = <&u3port1 PHY_TYPE_PCIE>; 256 phy-names = "pcie-phy1"; 257 bus-range = <0x00 0xff>; 258 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; 259 260 #interrupt-cells = <1>; 261 interrupt-map-mask = <0 0 0 7>; 262 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 263 <0 0 0 2 &pcie_intc1 1>, 264 <0 0 0 3 &pcie_intc1 2>, 265 <0 0 0 4 &pcie_intc1 3>; 266 pcie_intc1: interrupt-controller { 267 interrupt-controller; 268 #address-cells = <0>; 269 #interrupt-cells = <1>; 270 }; 271 }; 272 273 pcie@11700000 { 274 compatible = "mediatek,mt2712-pcie"; 275 device_type = "pci"; 276 reg = <0 0x11700000 0 0x1000>; 277 reg-names = "port0"; 278 linux,pci-domain = <0>; 279 #address-cells = <3>; 280 #size-cells = <2>; 281 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-names = "pcie_irq"; 283 clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ 284 <&pericfg>; /* CLK_PERI_PCIE0 */ 285 clock-names = "sys_ck0", "ahb_ck0"; 286 phys = <&u3port0 PHY_TYPE_PCIE>; 287 phy-names = "pcie-phy0"; 288 bus-range = <0x00 0xff>; 289 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 290 291 #interrupt-cells = <1>; 292 interrupt-map-mask = <0 0 0 7>; 293 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 294 <0 0 0 2 &pcie_intc0 1>, 295 <0 0 0 3 &pcie_intc0 2>, 296 <0 0 0 4 &pcie_intc0 3>; 297 pcie_intc0: interrupt-controller { 298 interrupt-controller; 299 #address-cells = <0>; 300 #interrupt-cells = <1>; 301 }; 302 }; 303 }; 304 305 # MT7622 306 - | 307 #include <dt-bindings/interrupt-controller/arm-gic.h> 308 #include <dt-bindings/interrupt-controller/irq.h> 309 #include <dt-bindings/power/mt7622-power.h> 310 311 soc_2 { 312 #address-cells = <2>; 313 #size-cells = <2>; 314 315 pcie@1a143000 { 316 compatible = "mediatek,mt7622-pcie"; 317 device_type = "pci"; 318 reg = <0 0x1a143000 0 0x1000>; 319 reg-names = "port0"; 320 linux,pci-domain = <0>; 321 #address-cells = <3>; 322 #size-cells = <2>; 323 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 324 interrupt-names = "pcie_irq"; 325 clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ 326 <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ 327 <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ 328 <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ 329 <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ 330 <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ 331 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", 332 "axi_ck0", "obff_ck0", "pipe_ck0"; 333 334 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 335 bus-range = <0x00 0xff>; 336 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; 337 338 #interrupt-cells = <1>; 339 interrupt-map-mask = <0 0 0 7>; 340 interrupt-map = <0 0 0 1 &pcie_intc0_1 0>, 341 <0 0 0 2 &pcie_intc0_1 1>, 342 <0 0 0 3 &pcie_intc0_1 2>, 343 <0 0 0 4 &pcie_intc0_1 3>; 344 pcie_intc0_1: interrupt-controller { 345 interrupt-controller; 346 #address-cells = <0>; 347 #interrupt-cells = <1>; 348 }; 349 }; 350 351 pcie@1a145000 { 352 compatible = "mediatek,mt7622-pcie"; 353 device_type = "pci"; 354 reg = <0 0x1a145000 0 0x1000>; 355 reg-names = "port1"; 356 linux,pci-domain = <1>; 357 #address-cells = <3>; 358 #size-cells = <2>; 359 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 360 interrupt-names = "pcie_irq"; 361 clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ 362 /* designer has connect RC1 with p0_ahb clock */ 363 <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ 364 <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ 365 <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ 366 <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ 367 <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ 368 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", 369 "axi_ck1", "obff_ck1", "pipe_ck1"; 370 371 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 372 bus-range = <0x00 0xff>; 373 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; 374 375 #interrupt-cells = <1>; 376 interrupt-map-mask = <0 0 0 7>; 377 interrupt-map = <0 0 0 1 &pcie_intc1_1 0>, 378 <0 0 0 2 &pcie_intc1_1 1>, 379 <0 0 0 3 &pcie_intc1_1 2>, 380 <0 0 0 4 &pcie_intc1_1 3>; 381 pcie_intc1_1: interrupt-controller { 382 interrupt-controller; 383 #address-cells = <0>; 384 #interrupt-cells = <1>; 385 }; 386 }; 387 }; 388 389 # AN7583 390 - | 391 #include <dt-bindings/interrupt-controller/irq.h> 392 #include <dt-bindings/interrupt-controller/arm-gic.h> 393 #include <dt-bindings/clock/en7523-clk.h> 394 395 soc_3 { 396 #address-cells = <2>; 397 #size-cells = <2>; 398 399 pcie@1fa92000 { 400 compatible = "airoha,an7583-pcie"; 401 device_type = "pci"; 402 linux,pci-domain = <1>; 403 #address-cells = <3>; 404 #size-cells = <2>; 405 406 reg = <0x0 0x1fa92000 0x0 0x1670>; 407 reg-names = "port1"; 408 409 clocks = <&scuclk EN7523_CLK_PCIE>; 410 clock-names = "sys_ck1"; 411 412 phys = <&pciephy>; 413 phy-names = "pcie-phy1"; 414 415 ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>; 416 417 resets = <&scuclk>; /* AN7583_PCIE1_RST */ 418 reset-names = "pcie-rst1"; 419 420 mediatek,pbus-csr = <&pbus_csr 0x8 0xc>; 421 422 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 423 interrupt-names = "pcie_irq"; 424 bus-range = <0x00 0xff>; 425 #interrupt-cells = <1>; 426 interrupt-map-mask = <0 0 0 7>; 427 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 428 <0 0 0 2 &pcie_intc1 1>, 429 <0 0 0 3 &pcie_intc1 2>, 430 <0 0 0 4 &pcie_intc1 3>; 431 432 pcie_intc1_4: interrupt-controller { 433 interrupt-controller; 434 #address-cells = <0>; 435 #interrupt-cells = <1>; 436 }; 437 }; 438 }; 439