xref: /linux/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml (revision 0bd0a41a5120f78685a132834865b0a631b9026a) 
1*9e71c414SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*9e71c414SRob Herring (Arm)%YAML 1.2
3*9e71c414SRob Herring (Arm)---
4*9e71c414SRob Herring (Arm)$id: http://devicetree.org/schemas/pci/marvell,armada-3700-pcie.yaml#
5*9e71c414SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml#
6*9e71c414SRob Herring (Arm)
7*9e71c414SRob Herring (Arm)title: Marvell Armada 3700 (Aardvark) PCIe Controller
8*9e71c414SRob Herring (Arm)
9*9e71c414SRob Herring (Arm)maintainers:
10*9e71c414SRob Herring (Arm)  - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
11*9e71c414SRob Herring (Arm)  - Pali Rohár <pali@kernel.org>
12*9e71c414SRob Herring (Arm)
13*9e71c414SRob Herring (Arm)allOf:
14*9e71c414SRob Herring (Arm)  - $ref: /schemas/pci/pci-host-bridge.yaml#
15*9e71c414SRob Herring (Arm)
16*9e71c414SRob Herring (Arm)properties:
17*9e71c414SRob Herring (Arm)  compatible:
18*9e71c414SRob Herring (Arm)    const: marvell,armada-3700-pcie
19*9e71c414SRob Herring (Arm)
20*9e71c414SRob Herring (Arm)  reg:
21*9e71c414SRob Herring (Arm)    maxItems: 1
22*9e71c414SRob Herring (Arm)
23*9e71c414SRob Herring (Arm)  clocks:
24*9e71c414SRob Herring (Arm)    maxItems: 1
25*9e71c414SRob Herring (Arm)
26*9e71c414SRob Herring (Arm)  interrupts:
27*9e71c414SRob Herring (Arm)    maxItems: 1
28*9e71c414SRob Herring (Arm)
29*9e71c414SRob Herring (Arm)  msi-controller: true
30*9e71c414SRob Herring (Arm)
31*9e71c414SRob Herring (Arm)  msi-parent:
32*9e71c414SRob Herring (Arm)    maxItems: 1
33*9e71c414SRob Herring (Arm)
34*9e71c414SRob Herring (Arm)  phys:
35*9e71c414SRob Herring (Arm)    maxItems: 1
36*9e71c414SRob Herring (Arm)
37*9e71c414SRob Herring (Arm)  reset-gpios:
38*9e71c414SRob Herring (Arm)    description: PCIe reset GPIO signals.
39*9e71c414SRob Herring (Arm)
40*9e71c414SRob Herring (Arm)  interrupt-controller:
41*9e71c414SRob Herring (Arm)    type: object
42*9e71c414SRob Herring (Arm)    additionalProperties: false
43*9e71c414SRob Herring (Arm)
44*9e71c414SRob Herring (Arm)    properties:
45*9e71c414SRob Herring (Arm)      interrupt-controller: true
46*9e71c414SRob Herring (Arm)
47*9e71c414SRob Herring (Arm)      '#interrupt-cells':
48*9e71c414SRob Herring (Arm)        const: 1
49*9e71c414SRob Herring (Arm)
50*9e71c414SRob Herring (Arm)    required:
51*9e71c414SRob Herring (Arm)      - interrupt-controller
52*9e71c414SRob Herring (Arm)      - '#interrupt-cells'
53*9e71c414SRob Herring (Arm)
54*9e71c414SRob Herring (Arm)required:
55*9e71c414SRob Herring (Arm)  - compatible
56*9e71c414SRob Herring (Arm)  - reg
57*9e71c414SRob Herring (Arm)  - interrupts
58*9e71c414SRob Herring (Arm)  - '#interrupt-cells'
59*9e71c414SRob Herring (Arm)
60*9e71c414SRob Herring (Arm)unevaluatedProperties: false
61*9e71c414SRob Herring (Arm)
62*9e71c414SRob Herring (Arm)examples:
63*9e71c414SRob Herring (Arm)  - |
64*9e71c414SRob Herring (Arm)    #include <dt-bindings/interrupt-controller/arm-gic.h>
65*9e71c414SRob Herring (Arm)    #include <dt-bindings/gpio/gpio.h>
66*9e71c414SRob Herring (Arm)
67*9e71c414SRob Herring (Arm)    bus {
68*9e71c414SRob Herring (Arm)        #address-cells = <2>;
69*9e71c414SRob Herring (Arm)        #size-cells = <2>;
70*9e71c414SRob Herring (Arm)
71*9e71c414SRob Herring (Arm)        pcie@d0070000 {
72*9e71c414SRob Herring (Arm)            compatible = "marvell,armada-3700-pcie";
73*9e71c414SRob Herring (Arm)            device_type = "pci";
74*9e71c414SRob Herring (Arm)            reg = <0 0xd0070000 0 0x20000>;
75*9e71c414SRob Herring (Arm)            #address-cells = <3>;
76*9e71c414SRob Herring (Arm)            #size-cells = <2>;
77*9e71c414SRob Herring (Arm)            bus-range = <0x00 0xff>;
78*9e71c414SRob Herring (Arm)            interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
79*9e71c414SRob Herring (Arm)            msi-controller;
80*9e71c414SRob Herring (Arm)            msi-parent = <&pcie0>;
81*9e71c414SRob Herring (Arm)            ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000>,
82*9e71c414SRob Herring (Arm)                    <0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>;
83*9e71c414SRob Herring (Arm)
84*9e71c414SRob Herring (Arm)            #interrupt-cells = <1>;
85*9e71c414SRob Herring (Arm)            interrupt-map-mask = <0 0 0 7>;
86*9e71c414SRob Herring (Arm)            interrupt-map = <0 0 0 1 &pcie_intc 0>,
87*9e71c414SRob Herring (Arm)                            <0 0 0 2 &pcie_intc 1>,
88*9e71c414SRob Herring (Arm)                            <0 0 0 3 &pcie_intc 2>,
89*9e71c414SRob Herring (Arm)                            <0 0 0 4 &pcie_intc 3>;
90*9e71c414SRob Herring (Arm)            phys = <&comphy1 0>;
91*9e71c414SRob Herring (Arm)            max-link-speed = <2>;
92*9e71c414SRob Herring (Arm)            reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
93*9e71c414SRob Herring (Arm)
94*9e71c414SRob Herring (Arm)            pcie_intc: interrupt-controller {
95*9e71c414SRob Herring (Arm)                interrupt-controller;
96*9e71c414SRob Herring (Arm)                #interrupt-cells = <1>;
97*9e71c414SRob Herring (Arm)            };
98*9e71c414SRob Herring (Arm)        };
99*9e71c414SRob Herring (Arm)    };
100