xref: /linux/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml (revision 0bd0a41a5120f78685a132834865b0a631b9026a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/marvell,armada-3700-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell Armada 3700 (Aardvark) PCIe Controller
8
9maintainers:
10  - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
11  - Pali Rohár <pali@kernel.org>
12
13allOf:
14  - $ref: /schemas/pci/pci-host-bridge.yaml#
15
16properties:
17  compatible:
18    const: marvell,armada-3700-pcie
19
20  reg:
21    maxItems: 1
22
23  clocks:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  msi-controller: true
30
31  msi-parent:
32    maxItems: 1
33
34  phys:
35    maxItems: 1
36
37  reset-gpios:
38    description: PCIe reset GPIO signals.
39
40  interrupt-controller:
41    type: object
42    additionalProperties: false
43
44    properties:
45      interrupt-controller: true
46
47      '#interrupt-cells':
48        const: 1
49
50    required:
51      - interrupt-controller
52      - '#interrupt-cells'
53
54required:
55  - compatible
56  - reg
57  - interrupts
58  - '#interrupt-cells'
59
60unevaluatedProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/interrupt-controller/arm-gic.h>
65    #include <dt-bindings/gpio/gpio.h>
66
67    bus {
68        #address-cells = <2>;
69        #size-cells = <2>;
70
71        pcie@d0070000 {
72            compatible = "marvell,armada-3700-pcie";
73            device_type = "pci";
74            reg = <0 0xd0070000 0 0x20000>;
75            #address-cells = <3>;
76            #size-cells = <2>;
77            bus-range = <0x00 0xff>;
78            interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
79            msi-controller;
80            msi-parent = <&pcie0>;
81            ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000>,
82                    <0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>;
83
84            #interrupt-cells = <1>;
85            interrupt-map-mask = <0 0 0 7>;
86            interrupt-map = <0 0 0 1 &pcie_intc 0>,
87                            <0 0 0 2 &pcie_intc 1>,
88                            <0 0 0 3 &pcie_intc 2>,
89                            <0 0 0 4 &pcie_intc 3>;
90            phys = <&comphy1 0>;
91            max-link-speed = <2>;
92            reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
93
94            pcie_intc: interrupt-controller {
95                interrupt-controller;
96                #interrupt-cells = <1>;
97            };
98        };
99    };
100