1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/eswin,pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ESWIN PCIe Root Complex 8 9maintainers: 10 - Yu Ning <ningyu@eswincomputing.com> 11 - Senchuan Zhang <zhangsenchuan@eswincomputing.com> 12 - Yanghui Ou <ouyanghui@eswincomputing.com> 13 14description: 15 ESWIN SoCs PCIe Root Complex is based on the Synopsys DesignWare PCIe IP. 16 17properties: 18 compatible: 19 const: eswin,eic7700-pcie 20 21 reg: 22 maxItems: 3 23 24 reg-names: 25 items: 26 - const: dbi 27 - const: config 28 - const: elbi 29 30 ranges: 31 maxItems: 3 32 33 '#interrupt-cells': 34 const: 1 35 36 interrupt-names: 37 items: 38 - const: msi 39 - const: inta 40 - const: intb 41 - const: intc 42 - const: intd 43 44 interrupt-map: 45 maxItems: 4 46 47 interrupt-map-mask: 48 items: 49 - const: 0 50 - const: 0 51 - const: 0 52 - const: 7 53 54 clocks: 55 maxItems: 4 56 57 clock-names: 58 items: 59 - const: mstr 60 - const: dbi 61 - const: phy_reg 62 - const: aux 63 64 resets: 65 maxItems: 2 66 67 reset-names: 68 items: 69 - const: dbi 70 - const: pwr 71 72patternProperties: 73 "^pcie@": 74 type: object 75 $ref: /schemas/pci/pci-pci-bridge.yaml# 76 77 properties: 78 reg: 79 maxItems: 1 80 81 num-lanes: 82 maximum: 4 83 84 resets: 85 maxItems: 1 86 87 reset-names: 88 items: 89 - const: perst 90 91 required: 92 - reg 93 - ranges 94 - num-lanes 95 - resets 96 - reset-names 97 98 unevaluatedProperties: false 99 100required: 101 - compatible 102 - reg 103 - ranges 104 - interrupts 105 - interrupt-names 106 - interrupt-map-mask 107 - interrupt-map 108 - '#interrupt-cells' 109 - clocks 110 - clock-names 111 - resets 112 - reset-names 113 114allOf: 115 - $ref: /schemas/pci/snps,dw-pcie.yaml# 116 117unevaluatedProperties: false 118 119examples: 120 - | 121 soc { 122 #address-cells = <2>; 123 #size-cells = <2>; 124 125 pcie@54000000 { 126 compatible = "eswin,eic7700-pcie"; 127 reg = <0x0 0x54000000 0x0 0x4000000>, 128 <0x0 0x40000000 0x0 0x800000>, 129 <0x0 0x50000000 0x0 0x100000>; 130 reg-names = "dbi", "config", "elbi"; 131 #address-cells = <3>; 132 #size-cells = <2>; 133 #interrupt-cells = <1>; 134 ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>, 135 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>, 136 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>; 137 bus-range = <0x00 0xff>; 138 clocks = <&clock 144>, 139 <&clock 145>, 140 <&clock 146>, 141 <&clock 147>; 142 clock-names = "mstr", "dbi", "phy_reg", "aux"; 143 resets = <&reset 97>, 144 <&reset 98>; 145 reset-names = "dbi", "pwr"; 146 interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>; 147 interrupt-names = "msi", "inta", "intb", "intc", "intd"; 148 interrupt-parent = <&plic>; 149 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 150 interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>, 151 <0x0 0x0 0x0 0x2 &plic 180>, 152 <0x0 0x0 0x0 0x3 &plic 181>, 153 <0x0 0x0 0x0 0x4 &plic 182>; 154 device_type = "pci"; 155 pcie@0 { 156 reg = <0x0 0x0 0x0 0x0 0x0>; 157 #address-cells = <3>; 158 #size-cells = <2>; 159 ranges; 160 device_type = "pci"; 161 num-lanes = <4>; 162 resets = <&reset 99>; 163 reset-names = "perst"; 164 }; 165 }; 166 }; 167