xref: /linux/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ASPEED PCIe Root Complex Controller
8
9maintainers:
10  - Jacky Chou <jacky_chou@aspeedtech.com>
11
12description:
13  The ASPEED PCIe Root Complex controller provides PCI Express Root Complex
14  functionality for ASPEED SoCs, such as the AST2600 and AST2700.
15  This controller enables connectivity to PCIe endpoint devices, supporting
16  memory and I/O windows, MSI and INTx interrupts, and integration with
17  the SoC's clock, reset, and pinctrl subsystems. On AST2600, the PCIe Root
18  Port device number is always 8.
19
20properties:
21  compatible:
22    enum:
23      - aspeed,ast2600-pcie
24      - aspeed,ast2700-pcie
25
26  reg:
27    maxItems: 1
28
29  ranges:
30    minItems: 2
31    maxItems: 2
32
33  interrupts:
34    maxItems: 1
35    description: INTx and MSI interrupt
36
37  resets:
38    items:
39      - description: PCIe controller reset
40
41  reset-names:
42    items:
43      - const: h2x
44
45  aspeed,ahbc:
46    $ref: /schemas/types.yaml#/definitions/phandle
47    description:
48      Phandle to the ASPEED AHB Controller (AHBC) syscon node.
49      This reference is used by the PCIe controller to access
50      system-level configuration registers related to the AHB bus.
51      To enable AHB access for the PCIe controller.
52
53  aspeed,pciecfg:
54    $ref: /schemas/types.yaml#/definitions/phandle
55    description:
56      Phandle to the ASPEED PCIe configuration syscon node.
57      This reference allows the PCIe controller to access
58      SoC-specific PCIe configuration registers. There are the others
59      functions such PCIe RC and PCIe EP will use this common register
60      to configure the SoC interfaces.
61
62  interrupt-controller: true
63
64patternProperties:
65  "^pcie@[0-9a-f]+,0$":
66    type: object
67    $ref: /schemas/pci/pci-pci-bridge.yaml#
68
69    properties:
70      reg:
71        maxItems: 1
72
73      resets:
74        items:
75          - description: PERST# signal
76
77      reset-names:
78        items:
79          - const: perst
80
81      clocks:
82        maxItems: 1
83
84      phys:
85        maxItems: 1
86
87    required:
88      - resets
89      - reset-names
90      - clocks
91      - phys
92      - ranges
93
94    unevaluatedProperties: false
95
96allOf:
97  - $ref: /schemas/pci/pci-host-bridge.yaml#
98  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
99  - if:
100      properties:
101        compatible:
102          contains:
103            const: aspeed,ast2600-pcie
104    then:
105      required:
106        - aspeed,ahbc
107    else:
108      properties:
109        aspeed,ahbc: false
110  - if:
111      properties:
112        compatible:
113          contains:
114            const: aspeed,ast2700-pcie
115    then:
116      required:
117        - aspeed,pciecfg
118    else:
119      properties:
120        aspeed,pciecfg: false
121
122required:
123  - reg
124  - interrupts
125  - bus-range
126  - ranges
127  - resets
128  - reset-names
129  - msi-controller
130  - interrupt-controller
131  - interrupt-map-mask
132  - interrupt-map
133
134unevaluatedProperties: false
135
136examples:
137  - |
138    #include <dt-bindings/interrupt-controller/arm-gic.h>
139    #include <dt-bindings/clock/ast2600-clock.h>
140
141    pcie0: pcie@1e770000 {
142      compatible = "aspeed,ast2600-pcie";
143      device_type = "pci";
144      reg = <0x1e770000 0x100>;
145      #address-cells = <3>;
146      #size-cells = <2>;
147      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
148      bus-range = <0x00 0xff>;
149
150      ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
151                0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>;
152
153      resets = <&syscon ASPEED_RESET_H2X>;
154      reset-names = "h2x";
155
156      #interrupt-cells = <1>;
157      msi-controller;
158
159      aspeed,ahbc = <&ahbc>;
160
161      interrupt-controller;
162      interrupt-map-mask = <0 0 0 7>;
163      interrupt-map = <0 0 0 1 &pcie0 0>,
164                      <0 0 0 2 &pcie0 1>,
165                      <0 0 0 3 &pcie0 2>,
166                      <0 0 0 4 &pcie0 3>;
167
168      pcie@8,0 {
169        compatible = "pciclass,0604";
170        reg = <0x00004000 0 0 0 0>;
171        #address-cells = <3>;
172        #size-cells = <2>;
173        device_type = "pci";
174        resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
175        reset-names = "perst";
176        clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
177        pinctrl-names = "default";
178        pinctrl-0 = <&pinctrl_pcierc1_default>;
179        phys = <&pcie_phy1>;
180        ranges;
181      };
182    };
183