1*12da6f08STudor Ambarus# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*12da6f08STudor Ambarus%YAML 1.2 3*12da6f08STudor Ambarus--- 4*12da6f08STudor Ambarus$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml# 5*12da6f08STudor Ambarus$schema: http://devicetree.org/meta-schemas/core.yaml# 6*12da6f08STudor Ambarus 7*12da6f08STudor Ambarustitle: Google GS101 OTP Controller 8*12da6f08STudor Ambarus 9*12da6f08STudor Ambarusmaintainers: 10*12da6f08STudor Ambarus - Tudor Ambarus <tudor.ambarus@linaro.org> 11*12da6f08STudor Ambarus 12*12da6f08STudor Ambarusdescription: | 13*12da6f08STudor Ambarus OTP controller drives a NVMEM memory where system or user specific data 14*12da6f08STudor Ambarus can be stored. The OTP controller register space is of interest as well 15*12da6f08STudor Ambarus because it contains dedicated registers where it stores the Product ID 16*12da6f08STudor Ambarus and the Chip ID (apart other things like TMU or ASV info). 17*12da6f08STudor Ambarus 18*12da6f08STudor AmbarusallOf: 19*12da6f08STudor Ambarus - $ref: nvmem.yaml# 20*12da6f08STudor Ambarus 21*12da6f08STudor Ambarusproperties: 22*12da6f08STudor Ambarus compatible: 23*12da6f08STudor Ambarus items: 24*12da6f08STudor Ambarus - const: google,gs101-otp 25*12da6f08STudor Ambarus 26*12da6f08STudor Ambarus clocks: 27*12da6f08STudor Ambarus maxItems: 1 28*12da6f08STudor Ambarus 29*12da6f08STudor Ambarus clock-names: 30*12da6f08STudor Ambarus const: pclk 31*12da6f08STudor Ambarus 32*12da6f08STudor Ambarus interrupts: 33*12da6f08STudor Ambarus maxItems: 1 34*12da6f08STudor Ambarus 35*12da6f08STudor Ambarus reg: 36*12da6f08STudor Ambarus maxItems: 1 37*12da6f08STudor Ambarus 38*12da6f08STudor Ambarus power-domains: 39*12da6f08STudor Ambarus maxItems: 1 40*12da6f08STudor Ambarus 41*12da6f08STudor Ambarusrequired: 42*12da6f08STudor Ambarus - compatible 43*12da6f08STudor Ambarus - reg 44*12da6f08STudor Ambarus - clocks 45*12da6f08STudor Ambarus - clock-names 46*12da6f08STudor Ambarus - interrupts 47*12da6f08STudor Ambarus 48*12da6f08STudor AmbarusunevaluatedProperties: false 49*12da6f08STudor Ambarus 50*12da6f08STudor Ambarusexamples: 51*12da6f08STudor Ambarus - | 52*12da6f08STudor Ambarus #include <dt-bindings/clock/google,gs101.h> 53*12da6f08STudor Ambarus #include <dt-bindings/interrupt-controller/arm-gic.h> 54*12da6f08STudor Ambarus 55*12da6f08STudor Ambarus efuse@10000000 { 56*12da6f08STudor Ambarus compatible = "google,gs101-otp"; 57*12da6f08STudor Ambarus reg = <0x10000000 0xf084>; 58*12da6f08STudor Ambarus clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>; 59*12da6f08STudor Ambarus clock-names = "pclk"; 60*12da6f08STudor Ambarus interrupts = <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>; 61*12da6f08STudor Ambarus }; 62