xref: /linux/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml (revision bdbddf72a2ab1cfea699959795d70df3931eefe7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Google GS101 OTP Controller
8
9maintainers:
10  - Tudor Ambarus <tudor.ambarus@linaro.org>
11
12description: |
13  OTP controller drives a NVMEM memory where system or user specific data
14  can be stored. The OTP controller register space is of interest as well
15  because it contains dedicated registers where it stores the Product ID
16  and the Chip ID (apart other things like TMU or ASV info).
17
18allOf:
19  - $ref: nvmem.yaml#
20
21properties:
22  compatible:
23    items:
24      - const: google,gs101-otp
25
26  clocks:
27    maxItems: 1
28
29  clock-names:
30    const: pclk
31
32  interrupts:
33    maxItems: 1
34
35  reg:
36    maxItems: 1
37
38  power-domains:
39    maxItems: 1
40
41required:
42  - compatible
43  - reg
44  - clocks
45  - clock-names
46  - interrupts
47
48unevaluatedProperties: false
49
50examples:
51  - |
52    #include <dt-bindings/clock/google,gs101.h>
53    #include <dt-bindings/interrupt-controller/arm-gic.h>
54
55    efuse@10000000 {
56        compatible = "google,gs101-otp";
57        reg = <0x10000000 0xf084>;
58        clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>;
59        clock-names = "pclk";
60        interrupts = <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>;
61    };
62