xref: /linux/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml (revision 4f38da1f027ea2c9f01bb71daa7a299c191b6940) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/nvmem/airoha,an8855-efuse.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Airoha AN8855 Switch EFUSE
8
9maintainers:
10  - Christian Marangi <ansuelsmth@gmail.com>
11
12description:
13  Airoha AN8855 EFUSE used to calibrate internal PHYs and store additional
14  configuration info.
15
16$ref: nvmem.yaml#
17
18properties:
19  compatible:
20    const: airoha,an8855-efuse
21
22  '#nvmem-cell-cells':
23    const: 0
24
25required:
26  - compatible
27  - '#nvmem-cell-cells'
28
29unevaluatedProperties: false
30
31examples:
32  - |
33    efuse {
34        compatible = "airoha,an8855-efuse";
35
36        #nvmem-cell-cells = <0>;
37
38        nvmem-layout {
39            compatible = "fixed-layout";
40            #address-cells = <1>;
41            #size-cells = <1>;
42
43            shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
44               reg = <0xc 0x4>;
45            };
46
47            shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
48                reg = <0x10 0x4>;
49            };
50
51            shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
52                reg = <0x14 0x4>;
53            };
54
55            shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
56               reg = <0x18 0x4>;
57            };
58
59            shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
60               reg = <0x1c 0x4>;
61            };
62
63            shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
64               reg = <0x20 0x4>;
65            };
66
67            shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
68               reg = <0x24 0x4>;
69            };
70
71            shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
72               reg = <0x28 0x4>;
73            };
74
75            shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
76                reg = <0x2c 0x4>;
77            };
78
79            shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
80                reg = <0x30 0x4>;
81            };
82
83            shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
84                reg = <0x34 0x4>;
85            };
86
87            shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
88                reg = <0x38 0x4>;
89            };
90
91            shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
92                reg = <0x4c 0x4>;
93            };
94
95            shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
96                reg = <0x50 0x4>;
97            };
98
99            shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
100               reg = <0x54 0x4>;
101            };
102
103            shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
104               reg = <0x58 0x4>;
105            };
106
107            shift_sel_port4_tx_a: shift-sel-port4-tx-a@5c {
108                reg = <0x5c 0x4>;
109            };
110
111            shift_sel_port4_tx_b: shift-sel-port4-tx-b@60 {
112                reg = <0x60 0x4>;
113            };
114
115            shift_sel_port4_tx_c: shift-sel-port4-tx-c@64 {
116                reg = <0x64 0x4>;
117            };
118
119            shift_sel_port4_tx_d: shift-sel-port4-tx-d@68 {
120                reg = <0x68 0x4>;
121            };
122        };
123    };
124