1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/micrel.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Micrel KSZ series PHYs and switches 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Stefan Eichenberger <eichest@gmail.com> 12 13description: 14 The Micrel KSZ series contains different network phys and switches. 15 16properties: 17 compatible: 18 enum: 19 - ethernet-phy-id000e.7237 # KSZ8873MLL 20 - ethernet-phy-id0022.1430 # KSZ886X 21 - ethernet-phy-id0022.1435 # KSZ8863 22 - ethernet-phy-id0022.1510 # KSZ8041 23 - ethernet-phy-id0022.1537 # KSZ8041RNLI 24 - ethernet-phy-id0022.1550 # KSZ8051 25 - ethernet-phy-id0022.1555 # KSZ8021 26 - ethernet-phy-id0022.1556 # KSZ8031 27 - ethernet-phy-id0022.1560 # KSZ8081, KSZ8091 28 - ethernet-phy-id0022.1570 # KSZ8061 29 - ethernet-phy-id0022.161a # KSZ8001 30 - ethernet-phy-id0022.1720 # KS8737 31 32 micrel,fiber-mode: 33 type: boolean 34 description: | 35 If present the PHY is configured to operate in fiber mode. 36 37 The KSZ8041FTL variant supports fiber mode, enabled by the FXEN 38 boot strapping pin. It can't be determined from the PHY registers 39 whether the PHY is in fiber mode, so this boolean device tree 40 property can be used to describe it. 41 42 In fiber mode, auto-negotiation is disabled and the PHY can only 43 work in 100base-fx (full and half duplex) modes. 44 45 micrel,led-mode: 46 $ref: /schemas/types.yaml#/definitions/uint32 47 description: | 48 LED mode value to set for PHYs with configurable LEDs. 49 50 Configure the LED mode with single value. The list of PHYs and the 51 bits that are currently supported: 52 53 KSZ8001: register 0x1e, bits 15..14 54 KSZ8021: register 0x1f, bits 5..4 55 KSZ8031: register 0x1f, bits 5..4 56 KSZ8041: register 0x1e, bits 15..14 57 KSZ8041RNLI: register 0x1e, bits 15..14 58 KSZ8051: register 0x1f, bits 5..4 59 KSZ8081: register 0x1f, bits 5..4 60 KSZ8091: register 0x1f, bits 5..4 61 62 See the respective PHY datasheet for the mode values. 63 minimum: 0 64 maximum: 3 65 66allOf: 67 - $ref: ethernet-phy.yaml# 68 - if: 69 not: 70 properties: 71 compatible: 72 contains: 73 const: ethernet-phy-id0022.1510 74 then: 75 properties: 76 micrel,fiber-mode: false 77 - if: 78 not: 79 properties: 80 compatible: 81 contains: 82 enum: 83 - ethernet-phy-id0022.1510 84 - ethernet-phy-id0022.1537 85 - ethernet-phy-id0022.1550 86 - ethernet-phy-id0022.1555 87 - ethernet-phy-id0022.1556 88 - ethernet-phy-id0022.1560 89 - ethernet-phy-id0022.161a 90 then: 91 properties: 92 micrel,led-mode: false 93 - if: 94 properties: 95 compatible: 96 contains: 97 enum: 98 - ethernet-phy-id0022.1555 99 - ethernet-phy-id0022.1556 100 - ethernet-phy-id0022.1560 101 then: 102 properties: 103 clock-names: 104 const: rmii-ref 105 description: 106 The RMII reference input clock. Used to determine the XI input 107 clock. 108 micrel,rmii-reference-clock-select-25-mhz: 109 type: boolean 110 description: | 111 RMII Reference Clock Select bit selects 25 MHz mode 112 113 Setting the RMII Reference Clock Select bit enables 25 MHz rather 114 than 50 MHz clock mode. 115 116dependentRequired: 117 micrel,rmii-reference-clock-select-25-mhz: [ clock-names ] 118 119unevaluatedProperties: false 120 121examples: 122 - | 123 mdio { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 ethernet-phy@5 { 128 compatible = "ethernet-phy-id0022.1510"; 129 reg = <5>; 130 micrel,led-mode = <2>; 131 micrel,fiber-mode; 132 }; 133 }; 134