1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/micrel.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Micrel KSZ series PHYs and switches 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Stefan Eichenberger <eichest@gmail.com> 12 13description: 14 The Micrel KSZ series contains different network phys and switches. 15 16properties: 17 compatible: 18 enum: 19 - ethernet-phy-id000e.7237 # KSZ8873MLL 20 - ethernet-phy-id0022.1430 # KSZ886X 21 - ethernet-phy-id0022.1435 # KSZ8863 22 - ethernet-phy-id0022.1510 # KSZ8041 23 - ethernet-phy-id0022.1537 # KSZ8041RNLI 24 - ethernet-phy-id0022.1550 # KSZ8051 25 - ethernet-phy-id0022.1555 # KSZ8021 26 - ethernet-phy-id0022.1556 # KSZ8031 27 - ethernet-phy-id0022.1560 # KSZ8081, KSZ8091 28 - ethernet-phy-id0022.1570 # KSZ8061 29 - ethernet-phy-id0022.161a # KSZ8001 30 - ethernet-phy-id0022.1720 # KS8737 31 32 micrel,fiber-mode: 33 type: boolean 34 description: | 35 If present the PHY is configured to operate in fiber mode. 36 37 The KSZ8041FTL variant supports fiber mode, enabled by the FXEN 38 boot strapping pin. It can't be determined from the PHY registers 39 whether the PHY is in fiber mode, so this boolean device tree 40 property can be used to describe it. 41 42 In fiber mode, auto-negotiation is disabled and the PHY can only 43 work in 100base-fx (full and half duplex) modes. 44 45 micrel,led-mode: 46 $ref: /schemas/types.yaml#/definitions/uint32 47 description: | 48 LED mode value to set for PHYs with configurable LEDs. 49 50 Configure the LED mode with single value. The list of PHYs and the 51 bits that are currently supported: 52 53 KSZ8001: register 0x1e, bits 15..14 54 KSZ8041: register 0x1e, bits 15..14 55 KSZ8021: register 0x1f, bits 5..4 56 KSZ8031: register 0x1f, bits 5..4 57 KSZ8051: register 0x1f, bits 5..4 58 KSZ8081: register 0x1f, bits 5..4 59 KSZ8091: register 0x1f, bits 5..4 60 61 See the respective PHY datasheet for the mode values. 62 minimum: 0 63 maximum: 3 64 65allOf: 66 - $ref: ethernet-phy.yaml# 67 - if: 68 not: 69 properties: 70 compatible: 71 contains: 72 const: ethernet-phy-id0022.1510 73 then: 74 properties: 75 micrel,fiber-mode: false 76 - if: 77 not: 78 properties: 79 compatible: 80 contains: 81 enum: 82 - ethernet-phy-id0022.1510 83 - ethernet-phy-id0022.1555 84 - ethernet-phy-id0022.1556 85 - ethernet-phy-id0022.1550 86 - ethernet-phy-id0022.1560 87 - ethernet-phy-id0022.161a 88 then: 89 properties: 90 micrel,led-mode: false 91 - if: 92 properties: 93 compatible: 94 contains: 95 enum: 96 - ethernet-phy-id0022.1555 97 - ethernet-phy-id0022.1556 98 - ethernet-phy-id0022.1560 99 then: 100 properties: 101 clock-names: 102 const: rmii-ref 103 description: 104 The RMII reference input clock. Used to determine the XI input 105 clock. 106 micrel,rmii-reference-clock-select-25-mhz: 107 type: boolean 108 description: | 109 RMII Reference Clock Select bit selects 25 MHz mode 110 111 Setting the RMII Reference Clock Select bit enables 25 MHz rather 112 than 50 MHz clock mode. 113 114dependentRequired: 115 micrel,rmii-reference-clock-select-25-mhz: [ clock-names ] 116 117unevaluatedProperties: false 118 119examples: 120 - | 121 mdio { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 ethernet-phy@5 { 126 compatible = "ethernet-phy-id0022.1510"; 127 reg = <5>; 128 micrel,led-mode = <2>; 129 micrel,fiber-mode; 130 }; 131 }; 132