1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/fsl,gianfar.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Three-Speed Ethernet Controller (TSEC), "Gianfar" 8 9maintainers: 10 - J. Neuschäfer <j.ne@posteo.net> 11 12# This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because 13# both use compatible = "gianfar" (with different device_type values) 14select: 15 oneOf: 16 - properties: 17 compatible: 18 contains: 19 const: gianfar 20 device_type: 21 const: network 22 required: 23 - device_type 24 25 - properties: 26 compatible: 27 const: fsl,etsec2 28 29 required: 30 - compatible 31 32properties: 33 compatible: 34 enum: 35 - gianfar 36 - fsl,etsec2 37 38 device_type: 39 const: network 40 41 model: 42 enum: 43 - FEC 44 - TSEC 45 - eTSEC 46 47 reg: 48 maxItems: 1 49 50 ranges: true 51 52 "#address-cells": 53 enum: [ 1, 2 ] 54 55 "#size-cells": 56 enum: [ 1, 2 ] 57 58 cell-index: 59 $ref: /schemas/types.yaml#/definitions/uint32 60 61 interrupts: 62 minItems: 1 63 items: 64 - description: Transmit interrupt or single combined interrupt 65 - description: Receive interrupt 66 - description: Error interrupt 67 68 dma-coherent: true 69 70 fsl,magic-packet: 71 type: boolean 72 description: 73 If present, indicates that the hardware supports waking up via magic packet. 74 75 fsl,wake-on-filer: 76 type: boolean 77 description: 78 If present, indicates that the hardware supports waking up by Filer 79 General Purpose Interrupt (FGPI) asserted on the Rx int line. This is 80 an advanced power management capability allowing certain packet types 81 (user) defined by filer rules to wake up the system. 82 83 bd-stash: 84 type: boolean 85 description: 86 If present, indicates that the hardware supports stashing buffer 87 descriptors in the L2. 88 89 rx-stash-len: 90 $ref: /schemas/types.yaml#/definitions/uint32 91 description: 92 Denotes the number of bytes of a received buffer to stash in the L2. 93 94 rx-stash-idx: 95 $ref: /schemas/types.yaml#/definitions/uint32 96 description: 97 Denotes the index of the first byte from the received buffer to stash in 98 the L2. 99 100 fsl,num_rx_queues: 101 $ref: /schemas/types.yaml#/definitions/uint32 102 description: Number of receive queues 103 const: 8 104 105 fsl,num_tx_queues: 106 $ref: /schemas/types.yaml#/definitions/uint32 107 description: Number of transmit queues 108 const: 8 109 110 tbi-handle: 111 $ref: /schemas/types.yaml#/definitions/phandle 112 description: Reference (phandle) to the TBI node 113 114required: 115 - compatible 116 - model 117 118patternProperties: 119 "^mdio@[0-9a-f]+$": 120 $ref: /schemas/net/fsl,gianfar-mdio.yaml# 121 122allOf: 123 - $ref: ethernet-controller.yaml# 124 125 # eTSEC2 controller nodes have "queue group" subnodes and don't need a "reg" 126 # property. 127 - if: 128 properties: 129 compatible: 130 contains: 131 const: fsl,etsec2 132 then: 133 patternProperties: 134 "^queue-group@[0-9a-f]+$": 135 type: object 136 137 properties: 138 reg: 139 maxItems: 1 140 141 interrupts: 142 items: 143 - description: Transmit interrupt 144 - description: Receive interrupt 145 - description: Error interrupt 146 147 required: 148 - reg 149 - interrupts 150 151 additionalProperties: false 152 else: 153 required: 154 - reg 155 156 # TSEC and eTSEC devices require three interrupts 157 - if: 158 properties: 159 model: 160 contains: 161 enum: [ TSEC, eTSEC ] 162 then: 163 properties: 164 interrupts: 165 items: 166 - description: Transmit interrupt 167 - description: Receive interrupt 168 - description: Error interrupt 169 170 171 172unevaluatedProperties: false 173 174examples: 175 - | 176 ethernet@24000 { 177 device_type = "network"; 178 model = "TSEC"; 179 compatible = "gianfar"; 180 reg = <0x24000 0x1000>; 181 local-mac-address = [ 00 00 00 00 00 00 ]; 182 interrupts = <29 2>, <30 2>, <34 2>; 183 interrupt-parent = <&mpic>; 184 phy-handle = <&phy0>; 185 }; 186 187 - | 188 #include <dt-bindings/interrupt-controller/irq.h> 189 190 ethernet@24000 { 191 compatible = "gianfar"; 192 reg = <0x24000 0x1000>; 193 ranges = <0x0 0x24000 0x1000>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 cell-index = <0>; 197 device_type = "network"; 198 model = "eTSEC"; 199 local-mac-address = [ 00 00 00 00 00 00 ]; 200 interrupts = <32 IRQ_TYPE_LEVEL_LOW>, 201 <33 IRQ_TYPE_LEVEL_LOW>, 202 <34 IRQ_TYPE_LEVEL_LOW>; 203 interrupt-parent = <&ipic>; 204 205 mdio@520 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 compatible = "fsl,gianfar-mdio"; 209 reg = <0x520 0x20>; 210 }; 211 }; 212 213 - | 214 #include <dt-bindings/interrupt-controller/irq.h> 215 #include <dt-bindings/interrupt-controller/arm-gic.h> 216 217 bus { 218 #address-cells = <2>; 219 #size-cells = <2>; 220 221 ethernet { 222 compatible = "fsl,etsec2"; 223 ranges; 224 device_type = "network"; 225 #address-cells = <2>; 226 #size-cells = <2>; 227 interrupt-parent = <&gic>; 228 model = "eTSEC"; 229 fsl,magic-packet; 230 dma-coherent; 231 232 queue-group@2d10000 { 233 reg = <0x0 0x2d10000 0x0 0x1000>; 234 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 237 }; 238 239 queue-group@2d14000 { 240 reg = <0x0 0x2d14000 0x0 0x1000>; 241 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 244 }; 245 }; 246 }; 247 248... 249