xref: /linux/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml (revision 24f171c7e145f43b9f187578e89b0982ce87e54c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/motorcomm,yt921x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Motorcomm YT921x Ethernet switch family
8
9maintainers:
10  - David Yang <mmyangfl@gmail.com>
11
12description: |
13  The Motorcomm YT921x series is a family of Ethernet switches with up to 8
14  internal GbE PHYs and up to 2 GMACs, including:
15
16    - YT9215S / YT9215RB / YT9215SC: 5 GbE PHYs (Port 0-4) + 2 GMACs (Port 8-9)
17    - YT9213NB: 2 GbE PHYs (Port 1/3) + 1 GMAC (Port 9)
18    - YT9214NB: 2 GbE PHYs (Port 1/3) + 2 GMACs (Port 8-9)
19    - YT9218N: 8 GbE PHYs (Port 0-7)
20    - YT9218MB: 8 GbE PHYs (Port 0-7) + 2 GMACs (Port 8-9)
21
22  Any port can be used as the CPU port.
23
24properties:
25  compatible:
26    const: motorcomm,yt9215
27
28  reg:
29    enum: [0x0, 0x1d]
30
31  reset-gpios:
32    maxItems: 1
33
34  mdio:
35    $ref: /schemas/net/mdio.yaml#
36    unevaluatedProperties: false
37    description:
38      Internal MDIO bus for the internal GbE PHYs. PHY 0-7 are used for Port
39      0-7 respectively.
40
41  mdio-external:
42    $ref: /schemas/net/mdio.yaml#
43    unevaluatedProperties: false
44    description:
45      External MDIO bus to access external components. External PHYs for GMACs
46      (Port 8-9) are expected to be connected to the external MDIO bus in
47      vendor's reference design, but that is not a hard limitation from the
48      chip.
49
50required:
51  - compatible
52  - reg
53
54allOf:
55  - $ref: dsa.yaml#/$defs/ethernet-ports
56
57unevaluatedProperties: false
58
59examples:
60  - |
61    #include <dt-bindings/gpio/gpio.h>
62
63    mdio {
64        #address-cells = <1>;
65        #size-cells = <0>;
66
67        switch@1d {
68            compatible = "motorcomm,yt9215";
69            /* default 0x1d, alternate 0x0 */
70            reg = <0x1d>;
71            reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
72
73            mdio {
74                #address-cells = <1>;
75                #size-cells = <0>;
76
77                sw_phy0: phy@0 {
78                    reg = <0x0>;
79                };
80
81                sw_phy1: phy@1 {
82                    reg = <0x1>;
83                };
84
85                sw_phy2: phy@2 {
86                    reg = <0x2>;
87                };
88
89                sw_phy3: phy@3 {
90                    reg = <0x3>;
91                };
92
93                sw_phy4: phy@4 {
94                    reg = <0x4>;
95                };
96            };
97
98            mdio-external {
99                #address-cells = <1>;
100                #size-cells = <0>;
101
102                phy1: phy@b {
103                    reg = <0xb>;
104                };
105            };
106
107            ethernet-ports {
108                #address-cells = <1>;
109                #size-cells = <0>;
110
111                ethernet-port@0 {
112                    reg = <0>;
113                    label = "lan1";
114                    phy-mode = "internal";
115                    phy-handle = <&sw_phy0>;
116                };
117
118                ethernet-port@1 {
119                    reg = <1>;
120                    label = "lan2";
121                    phy-mode = "internal";
122                    phy-handle = <&sw_phy1>;
123                };
124
125                ethernet-port@2 {
126                    reg = <2>;
127                    label = "lan3";
128                    phy-mode = "internal";
129                    phy-handle = <&sw_phy2>;
130                };
131
132                ethernet-port@3 {
133                    reg = <3>;
134                    label = "lan4";
135                    phy-mode = "internal";
136                    phy-handle = <&sw_phy3>;
137                };
138
139                ethernet-port@4 {
140                    reg = <4>;
141                    label = "lan5";
142                    phy-mode = "internal";
143                    phy-handle = <&sw_phy4>;
144                };
145
146                /* CPU port */
147                ethernet-port@8 {
148                    reg = <8>;
149                    phy-mode = "2500base-x";
150                    ethernet = <&eth0>;
151
152                    fixed-link {
153                        speed = <2500>;
154                        full-duplex;
155                    };
156                };
157
158                /* if external phy is connected to a MAC */
159                ethernet-port@9 {
160                    reg = <9>;
161                    label = "wan";
162                    phy-mode = "rgmii-id";
163                    phy-handle = <&phy1>;
164                };
165            };
166        };
167    };
168