xref: /linux/Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/maxlinear,mxl862xx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MaxLinear MxL862xx Ethernet Switch Family
8
9maintainers:
10  - Daniel Golle <daniel@makrotopia.org>
11
12description:
13  The MaxLinear MxL862xx switch family are multi-port Ethernet switches with
14  integrated 2.5GE PHYs. The MxL86252 has five PHY ports and the MxL86282
15  has eight PHY ports. Both models come with two 10 Gigabit/s SerDes
16  interfaces to be used to connect external PHYs or SFP cages, or as CPU
17  port.
18
19allOf:
20  - $ref: dsa.yaml#/$defs/ethernet-ports
21
22properties:
23  compatible:
24    enum:
25      - maxlinear,mxl86252
26      - maxlinear,mxl86282
27
28  reg:
29    maxItems: 1
30    description: MDIO address of the switch
31
32  mdio:
33    $ref: /schemas/net/mdio.yaml#
34    unevaluatedProperties: false
35
36required:
37  - compatible
38  - mdio
39  - reg
40
41unevaluatedProperties: false
42
43examples:
44  - |
45    mdio {
46        #address-cells = <1>;
47        #size-cells = <0>;
48
49        switch@0 {
50            compatible = "maxlinear,mxl86282";
51            reg = <0>;
52
53            ethernet-ports {
54                #address-cells = <1>;
55                #size-cells = <0>;
56
57                /* Microcontroller port */
58                port@0 {
59                    reg = <0>;
60                    status = "disabled";
61                };
62
63                port@1 {
64                    reg = <1>;
65                    phy-handle = <&phy0>;
66                    phy-mode = "internal";
67                };
68
69                port@2 {
70                    reg = <2>;
71                    phy-handle = <&phy1>;
72                    phy-mode = "internal";
73                };
74
75                port@3 {
76                    reg = <3>;
77                    phy-handle = <&phy2>;
78                    phy-mode = "internal";
79                };
80
81                port@4 {
82                    reg = <4>;
83                    phy-handle = <&phy3>;
84                    phy-mode = "internal";
85                };
86
87                port@5 {
88                    reg = <5>;
89                    phy-handle = <&phy4>;
90                    phy-mode = "internal";
91                };
92
93                port@6 {
94                    reg = <6>;
95                    phy-handle = <&phy5>;
96                    phy-mode = "internal";
97                };
98
99                port@7 {
100                    reg = <7>;
101                    phy-handle = <&phy6>;
102                    phy-mode = "internal";
103                };
104
105                port@8 {
106                    reg = <8>;
107                    phy-handle = <&phy7>;
108                    phy-mode = "internal";
109                };
110
111                port@9 {
112                    reg = <9>;
113                    label = "cpu";
114                    ethernet = <&gmac0>;
115                    phy-mode = "usxgmii";
116
117                    fixed-link {
118                        speed = <10000>;
119                        full-duplex;
120                    };
121                };
122            };
123
124            mdio {
125                #address-cells = <1>;
126                #size-cells = <0>;
127
128                phy0: ethernet-phy@0 {
129                    reg = <0>;
130                };
131
132                phy1: ethernet-phy@1 {
133                    reg = <1>;
134                };
135
136                phy2: ethernet-phy@2 {
137                    reg = <2>;
138                };
139
140                phy3: ethernet-phy@3 {
141                    reg = <3>;
142                };
143
144                phy4: ethernet-phy@4 {
145                    reg = <4>;
146                };
147
148                phy5: ethernet-phy@5 {
149                    reg = <5>;
150                };
151
152                phy6: ethernet-phy@6 {
153                    reg = <6>;
154                };
155
156                phy7: ethernet-phy@7 {
157                    reg = <7>;
158                };
159            };
160        };
161    };
162