xref: /linux/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml (revision a339dd699a7aa01bce4b38c8d81def310cf2bca0) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Altera SOCFPGA SoC DWMAC controller
8
9maintainers:
10  - Matthew Gerlach <matthew.gerlach@altera.com>
11
12description:
13  This binding describes the Altera SOCFPGA SoC implementation of the
14  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
15  of chips.
16  # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
17  # does not validate against net/snps,dwmac.yaml.
18
19select:
20  properties:
21    compatible:
22      contains:
23        enum:
24          - altr,socfpga-stmmac
25          - altr,socfpga-stmmac-a10-s10
26
27  required:
28    - compatible
29
30properties:
31  compatible:
32    oneOf:
33      - items:
34          - const: altr,socfpga-stmmac
35          - const: snps,dwmac-3.70a
36          - const: snps,dwmac
37      - items:
38          - const: altr,socfpga-stmmac-a10-s10
39          - const: snps,dwmac-3.72a
40          - const: snps,dwmac
41      - items:
42          - const: altr,socfpga-stmmac-a10-s10
43          - const: snps,dwmac-3.74a
44          - const: snps,dwmac
45
46  clocks:
47    minItems: 1
48    items:
49      - description: GMAC main clock
50      - description:
51          PTP reference clock. This clock is used for programming the
52          Timestamp Addend Register. If not passed then the system
53          clock will be used and this is fine on some platforms.
54
55  clock-names:
56    minItems: 1
57    items:
58      - const: stmmaceth
59      - const: ptp_ref
60
61  iommus:
62    minItems: 1
63    maxItems: 2
64
65  phy-mode:
66    enum:
67      - gmii
68      - mii
69      - rgmii
70      - rgmii-id
71      - rgmii-rxid
72      - rgmii-txid
73      - sgmii
74      - 1000base-x
75
76  rxc-skew-ps:
77    description: Skew control of RXC pad
78
79  rxd0-skew-ps:
80    description: Skew control of RX data 0 pad
81
82  rxd1-skew-ps:
83    description: Skew control of RX data 1 pad
84
85  rxd2-skew-ps:
86    description: Skew control of RX data 2 pad
87
88  rxd3-skew-ps:
89    description: Skew control of RX data 3 pad
90
91  rxdv-skew-ps:
92    description: Skew control of RX CTL pad
93
94  txc-skew-ps:
95    description: Skew control of TXC pad
96
97  txen-skew-ps:
98    description: Skew control of TXC pad
99
100  altr,emac-splitter:
101    $ref: /schemas/types.yaml#/definitions/phandle
102    description:
103      Should be the phandle to the emac splitter soft IP node if DWMAC
104      controller is connected an emac splitter.
105
106  altr,f2h_ptp_ref_clk:
107    $ref: /schemas/types.yaml#/definitions/phandle
108    description:
109      Phandle to Precision Time Protocol reference clock. This clock is
110      common to gmac instances and defaults to osc1.
111
112  altr,gmii-to-sgmii-converter:
113    $ref: /schemas/types.yaml#/definitions/phandle
114    description:
115      Should be the phandle to the gmii to sgmii converter soft IP.
116
117  altr,sysmgr-syscon:
118    $ref: /schemas/types.yaml#/definitions/phandle-array
119    description:
120      Should be the phandle to the system manager node that encompass
121      the glue register, the register offset, and the register shift.
122      On Cyclone5/Arria5, the register shift represents the PHY mode
123      bits, while on the Arria10/Stratix10/Agilex platforms, the
124      register shift represents bit for each emac to enable/disable
125      signals from the FPGA fabric to the EMAC modules.
126    items:
127      - items:
128          - description: phandle to the system manager node
129          - description: offset of the control register
130          - description: shift within the control register
131
132patternProperties:
133  "^mdio[0-9]$":
134    type: object
135
136required:
137  - compatible
138  - clocks
139  - clock-names
140  - altr,sysmgr-syscon
141
142allOf:
143  - $ref: snps,dwmac.yaml#
144
145unevaluatedProperties: false
146
147examples:
148
149  - |
150    #include <dt-bindings/interrupt-controller/arm-gic.h>
151    #include <dt-bindings/interrupt-controller/irq.h>
152    soc {
153        #address-cells = <1>;
154        #size-cells = <1>;
155        ethernet@ff700000 {
156            compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
157            "snps,dwmac";
158            altr,sysmgr-syscon = <&sysmgr 0x60 0>;
159            reg = <0xff700000 0x2000>;
160            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
161            interrupt-names = "macirq";
162            mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
163            clocks = <&emac_0_clk>;
164            clock-names = "stmmaceth";
165            phy-mode = "sgmii";
166        };
167    };
168