xref: /linux/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml (revision 5ef04a7b068cbb828eba226aacb42f880f7924d7) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Altera SOCFPGA SoC DWMAC controller
8
9maintainers:
10  - Matthew Gerlach <matthew.gerlach@altera.com>
11
12description:
13  This binding describes the Altera SOCFPGA SoC implementation of the
14  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
15  families of chips.
16  # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
17  # does not validate against net/snps,dwmac.yaml.
18
19select:
20  properties:
21    compatible:
22      contains:
23        enum:
24          - altr,socfpga-stmmac
25          - altr,socfpga-stmmac-a10-s10
26          - altr,socfpga-stmmac-agilex5
27
28  required:
29    - compatible
30
31properties:
32  compatible:
33    oneOf:
34      - items:
35          - const: altr,socfpga-stmmac
36          - const: snps,dwmac-3.70a
37          - const: snps,dwmac
38      - items:
39          - const: altr,socfpga-stmmac-a10-s10
40          - const: snps,dwmac-3.72a
41          - const: snps,dwmac
42      - items:
43          - const: altr,socfpga-stmmac-a10-s10
44          - const: snps,dwmac-3.74a
45          - const: snps,dwmac
46      - items:
47          - const: altr,socfpga-stmmac-agilex5
48          - const: snps,dwxgmac-2.10
49
50  clocks:
51    minItems: 1
52    items:
53      - description: GMAC main clock
54      - description:
55          PTP reference clock. This clock is used for programming the
56          Timestamp Addend Register. If not passed then the system
57          clock will be used and this is fine on some platforms.
58
59  clock-names:
60    minItems: 1
61    items:
62      - const: stmmaceth
63      - const: ptp_ref
64
65  interrupts:
66    maxItems: 1
67
68  interrupt-names:
69    items:
70      - const: macirq
71
72  iommus:
73    minItems: 1
74    maxItems: 2
75
76  phy-mode:
77    enum:
78      - gmii
79      - mii
80      - rgmii
81      - rgmii-id
82      - rgmii-rxid
83      - rgmii-txid
84      - sgmii
85      - 1000base-x
86
87  rxc-skew-ps:
88    description: Skew control of RXC pad
89
90  rxd0-skew-ps:
91    description: Skew control of RX data 0 pad
92
93  rxd1-skew-ps:
94    description: Skew control of RX data 1 pad
95
96  rxd2-skew-ps:
97    description: Skew control of RX data 2 pad
98
99  rxd3-skew-ps:
100    description: Skew control of RX data 3 pad
101
102  rxdv-skew-ps:
103    description: Skew control of RX CTL pad
104
105  txc-skew-ps:
106    description: Skew control of TXC pad
107
108  txen-skew-ps:
109    description: Skew control of TXC pad
110
111  altr,emac-splitter:
112    $ref: /schemas/types.yaml#/definitions/phandle
113    description:
114      Should be the phandle to the emac splitter soft IP node if DWMAC
115      controller is connected an emac splitter.
116
117  altr,f2h_ptp_ref_clk:
118    $ref: /schemas/types.yaml#/definitions/phandle
119    description:
120      Phandle to Precision Time Protocol reference clock. This clock is
121      common to gmac instances and defaults to osc1.
122
123  altr,gmii-to-sgmii-converter:
124    $ref: /schemas/types.yaml#/definitions/phandle
125    description:
126      Should be the phandle to the gmii to sgmii converter soft IP.
127
128  altr,sysmgr-syscon:
129    $ref: /schemas/types.yaml#/definitions/phandle-array
130    description:
131      Should be the phandle to the system manager node that encompass
132      the glue register, the register offset, and the register shift.
133      On Cyclone5/Arria5, the register shift represents the PHY mode
134      bits, while on the Arria10/Stratix10/Agilex platforms, the
135      register shift represents bit for each emac to enable/disable
136      signals from the FPGA fabric to the EMAC modules.
137    items:
138      - items:
139          - description: phandle to the system manager node
140          - description: offset of the control register
141          - description: shift within the control register
142
143patternProperties:
144  "^mdio[0-9]$":
145    type: object
146
147required:
148  - compatible
149  - clocks
150  - clock-names
151  - altr,sysmgr-syscon
152
153allOf:
154  - $ref: snps,dwmac.yaml#
155
156unevaluatedProperties: false
157
158examples:
159
160  - |
161    #include <dt-bindings/interrupt-controller/arm-gic.h>
162    #include <dt-bindings/interrupt-controller/irq.h>
163    soc {
164        #address-cells = <1>;
165        #size-cells = <1>;
166        ethernet@ff700000 {
167            compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
168            "snps,dwmac";
169            altr,sysmgr-syscon = <&sysmgr 0x60 0>;
170            reg = <0xff700000 0x2000>;
171            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
172            interrupt-names = "macirq";
173            mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
174            clocks = <&emac_0_clk>;
175            clock-names = "stmmaceth";
176            phy-mode = "sgmii";
177        };
178    };
179