1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/st,spear600-smi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STMicroelectronics SPEAr600 Serial Memory Interface (SMI) Controller 8 9maintainers: 10 - Richard Weinberger <richard@nod.at> 11 12description: 13 The SPEAr600 Serial Memory Interface (SMI) is a dedicated serial flash 14 controller supporting up to four chip selects for serial NOR flashes 15 connected in parallel. The controller is memory-mapped and the attached 16 flash devices appear in the CPU address space.The driver 17 (drivers/mtd/devices/spear_smi.c) probes the attached flashes 18 dynamically by sending commands (e.g., RDID) to each bank. 19 Flash sub nodes describe the memory range and optional per-flash 20 properties. 21 22allOf: 23 - $ref: mtd.yaml# 24 25properties: 26 compatible: 27 const: st,spear600-smi 28 29 reg: 30 maxItems: 1 31 32 interrupts: 33 maxItems: 1 34 35 "#address-cells": 36 const: 1 37 38 "#size-cells": 39 const: 1 40 41 clock-rate: 42 $ref: /schemas/types.yaml#/definitions/uint32 43 description: Functional clock rate of the SMI controller in Hz. 44 45 st,smi-fast-mode: 46 type: boolean 47 description: Indicates that the attached flash supports fast read mode. 48 49required: 50 - compatible 51 - reg 52 - clock-rate 53 54unevaluatedProperties: false 55 56examples: 57 - | 58 flash@fc000000 { 59 compatible = "st,spear600-smi"; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 reg = <0xfc000000 0x1000>; 63 interrupt-parent = <&vic1>; 64 interrupts = <12>; 65 clock-rate = <50000000>; /* 50 MHz */ 66 67 flash@f8000000 { 68 reg = <0xfc000000 0x1000>; 69 st,smi-fast-mode; 70 }; 71 }; 72... 73