1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/raw-nand-property.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Raw NAND Chip Common Properties 8 9maintainers: 10 - Miquel Raynal <miquel.raynal@bootlin.com> 11 12description: | 13 The ECC strength and ECC step size properties define the user 14 desires in terms of correction capability of a controller. Together, 15 they request the ECC engine to correct {strength} bit errors per 16 {size} bytes for a particular raw NAND chip. 17 18 The interpretation of these parameters is implementation-defined, so 19 not all implementations must support all possible 20 combinations. However, implementations are encouraged to further 21 specify the value(s) they support. 22 23properties: 24 nand-ecc-placement: 25 description: 26 Location of the ECC bytes. This location is unknown by default 27 but can be explicitly set to "oob", if all ECC bytes are 28 known to be stored in the OOB area, or "interleaved" if ECC 29 bytes will be interleaved with regular data in the main area. 30 $ref: /schemas/types.yaml#/definitions/string 31 enum: [ oob, interleaved ] 32 deprecated: true 33 34 nand-ecc-mode: 35 description: 36 Legacy ECC configuration mixing the ECC engine choice and 37 configuration. 38 $ref: /schemas/types.yaml#/definitions/string 39 enum: [none, soft, soft_bch, hw, hw_syndrome, on-die] 40 deprecated: true 41 42 nand-bus-width: 43 description: 44 Bus width to the NAND chip 45 $ref: /schemas/types.yaml#/definitions/uint32 46 enum: [8, 16] 47 default: 8 48 49 nand-on-flash-bbt: 50 description: 51 With this property, the OS will search the device for a Bad 52 Block Table (BBT). If not found, it will create one, reserve 53 a few blocks at the end of the device to store it and update 54 it as the device ages. Otherwise, the out-of-band area of a 55 few pages of all the blocks will be scanned at boot time to 56 find Bad Block Markers (BBM). These markers will help to 57 build a volatile BBT in RAM. 58 $ref: /schemas/types.yaml#/definitions/flag 59 60 nand-ecc-maximize: 61 description: 62 Whether or not the ECC strength should be maximized. The 63 maximum ECC strength is both controller and chip 64 dependent. The ECC engine has to select the ECC config 65 providing the best strength and taking the OOB area size 66 constraint into account. This is particularly useful when 67 only the in-band area is used by the upper layers, and you 68 want to make your NAND as reliable as possible. 69 $ref: /schemas/types.yaml#/definitions/flag 70 71 nand-is-boot-medium: 72 description: 73 Whether or not the NAND chip is a boot medium. Drivers might 74 use this information to select ECC algorithms supported by 75 the boot ROM or similar restrictions. 76 $ref: /schemas/types.yaml#/definitions/flag 77 78 nand-rb: 79 description: 80 Contains the native Ready/Busy IDs. 81 $ref: /schemas/types.yaml#/definitions/uint32-array 82 83 rb-gpios: 84 description: 85 Contains one or more GPIO descriptor (the numper of descriptor 86 depends on the number of R/B pins exposed by the flash) for the 87 Ready/Busy pins. Active state refers to the NAND ready state and 88 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. 89 90 wp-gpios: 91 description: 92 Contains one GPIO descriptor for the Write Protect pin. 93 Active state refers to the NAND Write Protect state and should be 94 set to GPIOD_ACTIVE_LOW unless the signal is inverted. 95 maxItems: 1 96 97# This is a generic file other binding inherit from and extend 98additionalProperties: true 99