1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MMC Controller & Slots Common Properties 8 9maintainers: 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 12description: 13 These properties are common to multiple MMC host controllers and the 14 possible slots or ports for multi-slot controllers. 15 16properties: 17 "#address-cells": 18 const: 1 19 description: 20 The cell is the SDIO function number if a function subnode is used. 21 22 "#size-cells": 23 const: 0 24 25 # Card Detection. 26 # If none of these properties are supplied, the host native card 27 # detect will be used. Only one of them should be provided. 28 29 broken-cd: 30 $ref: /schemas/types.yaml#/definitions/flag 31 description: 32 There is no card detection available; polling must be used. 33 34 cd-gpios: 35 maxItems: 1 36 description: 37 The card detection will be done using the GPIO provided. 38 39 non-removable: 40 $ref: /schemas/types.yaml#/definitions/flag 41 description: 42 Non-removable slot (like eMMC); assume always present. 43 44 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host 45 # controllers line polarity properties, we have to fix the meaning 46 # of the "normal" and "inverted" line levels. We choose to follow 47 # the SDHCI standard, which specifies both those lines as "active 48 # low." Therefore, using the "cd-inverted" property means, that the 49 # CD line is active high, i.e. it is high, when a card is 50 # inserted. Similar logic applies to the "wp-inverted" property. 51 # 52 # CD and WP lines can be implemented on the hardware in one of two 53 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or 54 # as dedicated pins. Polarity of dedicated pins can be specified, 55 # using *-inverted properties. GPIO polarity can also be specified 56 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the 57 # latter case. We choose to use the XOR logic for GPIO CD and WP 58 # lines. This means, the two properties are "superimposed," for 59 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the 60 # respective *-inverted property results in a 61 # double-inversion and actually means the "normal" line polarity is 62 # in effect. 63 wp-inverted: 64 $ref: /schemas/types.yaml#/definitions/flag 65 description: 66 The Write Protect line polarity is inverted. 67 68 cd-inverted: 69 $ref: /schemas/types.yaml#/definitions/flag 70 description: 71 The CD line polarity is inverted. 72 73 # Other properties 74 75 bus-width: 76 description: 77 Number of data lines. 78 $ref: /schemas/types.yaml#/definitions/uint32 79 enum: [1, 4, 8] 80 default: 1 81 82 max-frequency: 83 description: | 84 Maximum operating frequency of the bus: 85 - for eMMC, the maximum supported frequency is 200MHz, 86 - for SD/SDIO cards the SDR104 mode has a max supported 87 frequency of 208MHz, 88 - some mmc host controllers do support a max frequency up to 89 384MHz. 90 So, lets keep the maximum supported value here. 91 92 $ref: /schemas/types.yaml#/definitions/uint32 93 minimum: 400000 94 maximum: 384000000 95 96 max-sd-hs-hz: 97 description: | 98 Maximum frequency (in Hz) to be used for SD cards operating in 99 High-Speed (HS) mode. 100 minimum: 400000 101 maximum: 50000000 102 default: 50000000 103 104 disable-wp: 105 $ref: /schemas/types.yaml#/definitions/flag 106 description: 107 When set, no physical write-protect line is present. This 108 property should only be specified when the controller has a 109 dedicated write-protect detection logic. If a GPIO is always used 110 for the write-protect detection logic, it is sufficient to not 111 specify the wp-gpios property in the absence of a write-protect 112 line. Not used in combination with eMMC or SDIO. 113 114 wp-gpios: 115 maxItems: 1 116 description: 117 GPIO to use for the write-protect detection. 118 119 cd-debounce-delay-ms: 120 description: 121 Set delay time before detecting card after card insert 122 interrupt. 123 124 no-1-8-v: 125 $ref: /schemas/types.yaml#/definitions/flag 126 description: 127 When specified, denotes that 1.8V card voltage is not supported 128 on this system, even if the controller claims it. 129 130 cap-sd-highspeed: 131 $ref: /schemas/types.yaml#/definitions/flag 132 description: 133 SD high-speed timing is supported. 134 135 cap-mmc-highspeed: 136 $ref: /schemas/types.yaml#/definitions/flag 137 description: 138 MMC high-speed timing is supported. 139 140 sd-uhs-sdr12: 141 $ref: /schemas/types.yaml#/definitions/flag 142 description: 143 SD UHS SDR12 speed is supported. 144 145 sd-uhs-sdr25: 146 $ref: /schemas/types.yaml#/definitions/flag 147 description: 148 SD UHS SDR25 speed is supported. 149 150 sd-uhs-sdr50: 151 $ref: /schemas/types.yaml#/definitions/flag 152 description: 153 SD UHS SDR50 speed is supported. 154 155 sd-uhs-sdr104: 156 $ref: /schemas/types.yaml#/definitions/flag 157 description: 158 SD UHS SDR104 speed is supported. 159 160 sd-uhs-ddr50: 161 $ref: /schemas/types.yaml#/definitions/flag 162 description: 163 SD UHS DDR50 speed is supported. 164 165 cap-power-off-card: 166 $ref: /schemas/types.yaml#/definitions/flag 167 description: 168 Powering off the card is safe. 169 170 cap-mmc-hw-reset: 171 $ref: /schemas/types.yaml#/definitions/flag 172 description: 173 eMMC hardware reset is supported 174 175 cap-sdio-irq: 176 $ref: /schemas/types.yaml#/definitions/flag 177 description: 178 enable SDIO IRQ signalling on this interface 179 180 full-pwr-cycle: 181 $ref: /schemas/types.yaml#/definitions/flag 182 description: 183 Full power cycle of the card is supported. 184 185 full-pwr-cycle-in-suspend: 186 $ref: /schemas/types.yaml#/definitions/flag 187 description: 188 Full power cycle of the card in suspend is supported. 189 190 mmc-ddr-1_2v: 191 $ref: /schemas/types.yaml#/definitions/flag 192 description: 193 eMMC high-speed DDR mode (1.2V I/O) is supported. 194 195 mmc-ddr-1_8v: 196 $ref: /schemas/types.yaml#/definitions/flag 197 description: 198 eMMC high-speed DDR mode (1.8V I/O) is supported. 199 200 mmc-ddr-3_3v: 201 $ref: /schemas/types.yaml#/definitions/flag 202 description: 203 eMMC high-speed DDR mode (3.3V I/O) is supported. 204 205 mmc-hs200-1_2v: 206 $ref: /schemas/types.yaml#/definitions/flag 207 description: 208 eMMC HS200 mode (1.2V I/O) is supported. 209 210 mmc-hs200-1_8v: 211 $ref: /schemas/types.yaml#/definitions/flag 212 description: 213 eMMC HS200 mode (1.8V I/O) is supported. 214 215 mmc-hs400-1_2v: 216 $ref: /schemas/types.yaml#/definitions/flag 217 description: 218 eMMC HS400 mode (1.2V I/O) is supported. 219 220 mmc-hs400-1_8v: 221 $ref: /schemas/types.yaml#/definitions/flag 222 description: 223 eMMC HS400 mode (1.8V I/O) is supported. 224 225 mmc-hs400-enhanced-strobe: 226 $ref: /schemas/types.yaml#/definitions/flag 227 description: 228 eMMC HS400 enhanced strobe mode is supported 229 230 no-mmc-hs400: 231 $ref: /schemas/types.yaml#/definitions/flag 232 description: 233 All eMMC HS400 modes are not supported. 234 235 dsr: 236 description: 237 Value the card Driver Stage Register (DSR) should be programmed 238 with. 239 $ref: /schemas/types.yaml#/definitions/uint32 240 minimum: 0 241 maximum: 0xffff 242 243 no-sdio: 244 $ref: /schemas/types.yaml#/definitions/flag 245 description: 246 Controller is limited to send SDIO commands during 247 initialization. 248 249 no-sd: 250 $ref: /schemas/types.yaml#/definitions/flag 251 description: 252 Controller is limited to send SD commands during initialization. 253 254 no-mmc: 255 $ref: /schemas/types.yaml#/definitions/flag 256 description: 257 Controller is limited to send MMC commands during 258 initialization. 259 260 fixed-emmc-driver-type: 261 description: 262 For non-removable eMMC, enforce this driver type. The value is 263 the driver type as specified in the eMMC specification (table 264 206 in spec version 5.1) 265 $ref: /schemas/types.yaml#/definitions/uint32 266 minimum: 0 267 maximum: 4 268 269 post-power-on-delay-ms: 270 description: 271 It was invented for MMC pwrseq-simple which could be referred to 272 mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay 273 waiting for I/O signalling and card power supply to be stable, 274 regardless of whether pwrseq-simple is used. Default to 10ms if 275 not available. 276 default: 10 277 278 power-off-delay-us: 279 description: 280 Delay in microseconds after card power is deasserted during a power 281 cycle to allow time for proper power discharge. Larger values can be 282 configured to work around hardware issues such as slow RC discharge 283 on MMC VDD rails. 284 minimum: 0 285 maximum: 10000000 286 default: 1000 287 288 supports-cqe: 289 $ref: /schemas/types.yaml#/definitions/flag 290 description: 291 The presence of this property indicates that the corresponding 292 MMC host controller supports HW command queue feature. 293 294 disable-cqe-dcmd: 295 $ref: /schemas/types.yaml#/definitions/flag 296 description: 297 The presence of this property indicates that the MMC 298 controller\'s command queue engine (CQE) does not support direct 299 commands (DCMDs). 300 301 keep-power-in-suspend: 302 $ref: /schemas/types.yaml#/definitions/flag 303 description: 304 SDIO only. Preserves card power during a suspend/resume cycle. 305 306 wakeup-source: 307 $ref: /schemas/types.yaml#/definitions/flag 308 description: 309 SDIO only. Enables wake up of host system on SDIO IRQ assertion. 310 311 vmmc-supply: 312 description: 313 Supply for the card power 314 315 vqmmc-supply: 316 description: 317 Supply for the bus IO line power, such as a level shifter. 318 If the level shifter is controlled by a GPIO line, this shall 319 be modeled as a "regulator-fixed" with a GPIO line for 320 switching the level shifter on/off. 321 322 mmc-pwrseq: 323 $ref: /schemas/types.yaml#/definitions/phandle 324 description: 325 System-on-Chip designs may specify a specific MMC power 326 sequence. To successfully detect an (e)MMC/SD/SDIO card, that 327 power sequence must be maintained while initializing the card. 328 329patternProperties: 330 "^.*@[0-9]+$": 331 type: object 332 description: | 333 On embedded systems the cards connected to a host may need 334 additional properties. These can be specified in subnodes to the 335 host controller node. The subnodes are identified by the 336 standard \'reg\' property. Which information exactly can be 337 specified depends on the bindings for the SDIO function driver 338 for the subnode, as specified by the compatible string. 339 340 properties: 341 compatible: 342 description: 343 Name of SDIO function following generic names recommended 344 practice 345 346 reg: 347 items: 348 - minimum: 0 349 maximum: 7 350 description: 351 Must contain the SDIO function number of the function this 352 subnode describes. A value of 0 denotes the memory SD 353 function, values from 1 to 7 denote the SDIO functions. 354 355 required: 356 - reg 357 358 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": 359 $ref: /schemas/types.yaml#/definitions/uint32-array 360 361 minItems: 2 362 maxItems: 2 363 items: 364 minimum: 0 365 maximum: 359 366 description: 367 Set the clock (phase) delays which are to be configured in the 368 controller while switching to particular speed mode. These values 369 are in pair of degrees. 370 371dependencies: 372 cd-debounce-delay-ms: [ cd-gpios ] 373 fixed-emmc-driver-type: [ non-removable ] 374 375additionalProperties: true 376