xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml (revision 31b43c079f9aa55754c20404a42bca9a49e01f60) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra210 SoC Memory Controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: |
14  The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split
15  into two 32 bit channels to support LPDDR3 and LPDDR4 with x16 subpartitions.
16  The MC handles memory requests for 34-bit virtual addresses from internal
17  clients and arbitrates among them to allocate memory bandwidth.
18
19  Up to 8 GiB of physical memory can be supported. Security features such as
20  encryption of traffic to and from DRAM via general security apertures are
21  available for video and other secure applications.
22
23properties:
24  $nodename:
25    pattern: "^memory-controller@[0-9a-f]+$"
26
27  compatible:
28    items:
29      - enum:
30          - nvidia,tegra210-mc
31
32  reg:
33    maxItems: 1
34
35  interrupts:
36    maxItems: 1
37
38  clocks:
39    items:
40      - description: module clock
41
42  clock-names:
43    items:
44      - const: mc
45
46  "#iommu-cells":
47    const: 1
48
49  "#reset-cells":
50    const: 1
51
52required:
53  - compatible
54  - reg
55  - interrupts
56  - clocks
57  - clock-names
58  - "#iommu-cells"
59  - "#reset-cells"
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/tegra210-car.h>
66    #include <dt-bindings/interrupt-controller/arm-gic.h>
67
68    memory-controller@70019000 {
69        compatible = "nvidia,tegra210-mc";
70        reg = <0x70019000 0x1000>;
71        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
72        clocks = <&tegra_car TEGRA210_CLK_MC>;
73        clock-names = "mc";
74
75        #iommu-cells = <1>;
76        #reset-cells = <1>;
77    };
78