xref: /linux/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Common properties for SDRAM types
8
9description:
10  Different SDRAM types generally use the same properties and only differ in the
11  range of legal values for each. This file defines the common parts that can be
12  reused for each type. Nodes using this schema should generally be nested under
13  a SDRAM channel node.
14
15maintainers:
16  - Krzysztof Kozlowski <krzk@kernel.org>
17
18properties:
19  compatible:
20    description: |
21      Compatible strings can be either explicit vendor names and part numbers
22      (e.g. elpida,ECB240ABACN), or generated strings of the form
23      lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase
24      hexadecimal with leading zeroes, and A is lowercase ASCII.
25      For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
26      For LPDDR SDRAM:
27        - YY is the manufacturer ID (from MR5), 1 byte
28        - ZZZZ is the revision ID (from MR6 and MR7), 2 bytes
29      For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
30        - YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321
31        - AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348
32          without trailing spaces
33        - ZZ is the revision ID, 1 byte, from byte 349
34      The former form is useful when the SDRAM vendor and part number are
35      known, for example, when memory is soldered on the board. The latter
36      form is useful when SDRAM nodes are created at runtime by boot firmware
37      that doesn't have access to static part number information.
38
39  reg:
40    description:
41      The rank number of this memory rank when used as a subnode to an memory
42      channel.
43    minimum: 0
44    maximum: 3
45
46  revision-id:
47    $ref: /schemas/types.yaml#/definitions/uint32-array
48    description: |
49      SDRAM revision ID:
50        - LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.
51        - DDR4 SDRAM, decoded from the SPD from byte 349 according to
52          JEDEC SPD4.1.2.L-6, always 1 byte.
53      One byte per uint32 cell (e.g., <MR6 MR7>).
54    maxItems: 2
55    items:
56      minimum: 0
57      maximum: 255
58
59  density:
60    $ref: /schemas/types.yaml#/definitions/uint32
61    description: |
62      Density of the SDRAM chip in megabits:
63        - LPDDR SDRAM, decoded from Mode Register 8.
64        - DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to
65          JEDEC SPD4.1.2.L-6.
66    enum:
67      - 64
68      - 128
69      - 256
70      - 512
71      - 1024
72      - 2048
73      - 3072
74      - 4096
75      - 6144
76      - 8192
77      - 12288
78      - 16384
79      - 24576
80      - 32768
81
82  io-width:
83    $ref: /schemas/types.yaml#/definitions/uint32
84    description: |
85      I/O bus width in bits of the SDRAM chip:
86        - LPDDR SDRAM, decoded from Mode Register 8.
87        - DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to
88          JEDEC SPD4.1.2.L-6.
89    enum:
90      - 8
91      - 16
92      - 32
93
94additionalProperties: true
95