xref: /linux/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SDRAM channel with chip/rank topology description
8
9description:
10  A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely
11  independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory
12  chips to a host system. The main purpose of this node is to overall memory
13  topology of the system, including the amount of individual memory chips and
14  the ranks per chip.
15
16maintainers:
17  - Julius Werner <jwerner@chromium.org>
18
19properties:
20  $nodename:
21    pattern: "sdram-channel-[0-9]+$"
22
23  compatible:
24    enum:
25      - jedec,ddr4-channel
26      - jedec,lpddr2-channel
27      - jedec,lpddr3-channel
28      - jedec,lpddr4-channel
29      - jedec,lpddr5-channel
30
31  io-width:
32    description:
33      The number of DQ pins in the channel. If this number is different
34      from (a multiple of) the io-width of the SDRAM chip, that means that
35      multiple instances of that type of chip are wired in parallel on this
36      channel (with the channel's DQ pins split up between the different
37      chips, and the CA, CS, etc. pins of the different chips all shorted
38      together).  This means that the total physical memory controlled by a
39      channel is equal to the sum of the densities of each rank on the
40      connected SDRAM chip, times the io-width of the channel divided by
41      the io-width of the SDRAM chip.
42    enum:
43      - 8
44      - 16
45      - 32
46      - 64
47      - 128
48
49  "#address-cells":
50    const: 1
51
52  "#size-cells":
53    const: 0
54
55patternProperties:
56  "^rank@[0-9]+$":
57    type: object
58    description:
59      Each physical SDRAM chip may have one or more ranks. Ranks are
60      internal but fully independent sub-units of the chip. Each SDRAM bus
61      transaction on the channel targets exactly one rank, based on the
62      state of the CS pins. Different ranks may have different densities and
63      timing requirements.
64    required:
65      - reg
66
67allOf:
68  - if:
69      properties:
70        compatible:
71          contains:
72            const: jedec,ddr4-channel
73    then:
74      patternProperties:
75        "^rank@[0-9]+$":
76          $ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml#
77  - if:
78      properties:
79        compatible:
80          contains:
81            const: jedec,lpddr2-channel
82    then:
83      patternProperties:
84        "^rank@[0-9]+$":
85          $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
86  - if:
87      properties:
88        compatible:
89          contains:
90            const: jedec,lpddr3-channel
91    then:
92      patternProperties:
93        "^rank@[0-9]+$":
94          $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
95  - if:
96      properties:
97        compatible:
98          contains:
99            const: jedec,lpddr4-channel
100    then:
101      patternProperties:
102        "^rank@[0-9]+$":
103          $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
104  - if:
105      properties:
106        compatible:
107          contains:
108            const: jedec,lpddr5-channel
109    then:
110      patternProperties:
111        "^rank@[0-9]+$":
112          $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
113
114required:
115  - compatible
116  - io-width
117  - "#address-cells"
118  - "#size-cells"
119
120additionalProperties: false
121
122examples:
123  - |
124    sdram-channel-0 {
125      #address-cells = <1>;
126      #size-cells = <0>;
127      compatible = "jedec,lpddr3-channel";
128      io-width = <32>;
129
130      rank@0 {
131        compatible = "lpddr3-ff,0100", "jedec,lpddr3";
132        reg = <0>;
133        density = <8192>;
134        io-width = <16>;
135        revision-id = <1 0>;
136      };
137    };
138
139    sdram-channel-1 {
140      #address-cells = <1>;
141      #size-cells = <0>;
142      compatible = "jedec,lpddr4-channel";
143      io-width = <32>;
144
145      rank@0 {
146        compatible = "lpddr4-05,0301", "jedec,lpddr4";
147        reg = <0>;
148        density = <4096>;
149        io-width = <32>;
150        revision-id = <3 1>;
151      };
152
153      rank@1 {
154        compatible = "lpddr4-05,0301", "jedec,lpddr4";
155        reg = <1>;
156        density = <2048>;
157        io-width = <32>;
158        revision-id = <3 1>;
159      };
160    };
161