1*fa0321baSFlorian Fainelli# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*fa0321baSFlorian Fainelli%YAML 1.2 3*fa0321baSFlorian Fainelli--- 4*fa0321baSFlorian Fainelli$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml# 5*fa0321baSFlorian Fainelli$schema: http://devicetree.org/meta-schemas/core.yaml# 6*fa0321baSFlorian Fainelli 7*fa0321baSFlorian Fainellititle: Memory controller (MEMC) for Broadcom STB 8*fa0321baSFlorian Fainelli 9*fa0321baSFlorian Fainellimaintainers: 10*fa0321baSFlorian Fainelli - Florian Fainelli <f.fainelli@gmail.com> 11*fa0321baSFlorian Fainelli 12*fa0321baSFlorian Fainelliproperties: 13*fa0321baSFlorian Fainelli compatible: 14*fa0321baSFlorian Fainelli items: 15*fa0321baSFlorian Fainelli - enum: 16*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.1.x 17*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.0 18*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.1 19*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.2 20*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.3 21*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.5 22*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.6 23*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.7 24*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.2.8 25*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.3.0 26*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-b.3.1 27*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-c.1.0 28*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-c.1.1 29*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-c.1.2 30*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-c.1.3 31*fa0321baSFlorian Fainelli - brcm,brcmstb-memc-ddr-rev-c.1.4 32*fa0321baSFlorian Fainelli - const: brcm,brcmstb-memc-ddr 33*fa0321baSFlorian Fainelli 34*fa0321baSFlorian Fainelli reg: 35*fa0321baSFlorian Fainelli maxItems: 1 36*fa0321baSFlorian Fainelli 37*fa0321baSFlorian Fainelli clock-frequency: 38*fa0321baSFlorian Fainelli description: DDR PHY frequency in Hz 39*fa0321baSFlorian Fainelli 40*fa0321baSFlorian Fainellirequired: 41*fa0321baSFlorian Fainelli - compatible 42*fa0321baSFlorian Fainelli - reg 43*fa0321baSFlorian Fainelli 44*fa0321baSFlorian FainelliadditionalProperties: false 45*fa0321baSFlorian Fainelli 46*fa0321baSFlorian Fainelliexamples: 47*fa0321baSFlorian Fainelli - | 48*fa0321baSFlorian Fainelli memory-controller@9902000 { 49*fa0321baSFlorian Fainelli compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr"; 50*fa0321baSFlorian Fainelli reg = <0x9902000 0x600>; 51*fa0321baSFlorian Fainelli clock-frequency = <2133000000>; 52*fa0321baSFlorian Fainelli }; 53