1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/media/ti,vip.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Texas Instruments DRA7x Video Input Port (VIP) 9 10maintainers: 11 - Yemike Abhilash Chandra <y-abhilashchandra@ti.com> 12 13description: |- 14 Video Input Port (VIP) can be found on devices such as DRA7xx and 15 provides the system interface and the processing capability to 16 connect parallel image-sensor as well as BT.656/1120 capable encoder 17 chip to DRA7x device. 18 19 Each VIP instance supports 2 independently configurable external 20 video input capture slices (Slice 0 and Slice 1) each providing 21 up to two video input ports (Port A and Port B). 22 23properties: 24 compatible: 25 enum: 26 - ti,dra7-vip 27 28 reg: 29 maxItems: 1 30 31 interrupts: 32 items: 33 - description: IRQ index 0 is used for Slice0 interrupts 34 - description: IRQ index 1 is used for Slice1 interrupts 35 36 ti,ctrl-module: 37 description: 38 Reference to the device control module that provides clock-edge 39 inversion control for VIP ports. These controls allow the 40 VIP to sample pixel data on the correct clock edge. 41 $ref: /schemas/types.yaml#/definitions/phandle-array 42 items: 43 items: 44 - description: phandle to device control module 45 - description: offset to the CTRL_CORE_SMA_SW_1 register 46 - description: Bit field to slice 0 port A 47 - description: Bit field to slice 0 port B 48 - description: Bit field to slice 1 port A 49 - description: Bit field to slice 1 port B 50 maxItems: 1 51 52 ports: 53 $ref: /schemas/graph.yaml#/properties/ports 54 55 patternProperties: 56 '^port@[0-3]$': 57 $ref: /schemas/graph.yaml#/$defs/port-base 58 unevaluatedProperties: false 59 description: | 60 Each VIP instance supports 2 independently configurable external video 61 input capture slices (Slice 0 and Slice 1) each providing up to two video 62 input ports (Port A and Port B). These ports represent the following 63 port@0 -> Slice 0 Port A 64 port@1 -> Slice 0 Port B 65 port@2 -> Slice 1 Port A 66 port@3 -> Slice 1 Port B 67 68 properties: 69 endpoint: 70 $ref: /schemas/media/video-interfaces.yaml# 71 unevaluatedProperties: false 72 73 properties: 74 bus-width: 75 enum: [8, 16, 24] 76 default: 8 77 78required: 79 - compatible 80 - reg 81 - interrupts 82 - ti,ctrl-module 83 - ports 84 85additionalProperties: false 86 87examples: 88 - | 89 #include <dt-bindings/interrupt-controller/arm-gic.h> 90 #include <dt-bindings/interrupt-controller/irq.h> 91 92 video@48970000 { 93 compatible = "ti,dra7-vip"; 94 reg = <0x48970000 0x1000>; 95 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 97 ti,ctrl-module = <&scm_conf 0x534 0x0 0x2 0x1 0x3>; 98 99 ports { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 vin1a: port@0 { 104 reg = <0>; 105 106 vin1a_ep: endpoint { 107 remote-endpoint = <&camera1>; 108 hsync-active = <1>; 109 vsync-active = <1>; 110 pclk-sample = <0>; 111 bus-width = <8>; 112 }; 113 }; 114 115 vin1b: port@1 { 116 reg = <1>; 117 118 vin1b_ep: endpoint { 119 remote-endpoint = <&camera2>; 120 hsync-active = <1>; 121 vsync-active = <1>; 122 pclk-sample = <0>; 123 bus-width = <8>; 124 }; 125 }; 126 127 vin2a: port@2 { 128 reg = <2>; 129 130 vin2a_ep: endpoint { 131 remote-endpoint = <&camera3>; 132 hsync-active = <1>; 133 vsync-active = <1>; 134 pclk-sample = <0>; 135 bus-width = <16>; 136 }; 137 }; 138 139 vin2b: port@3 { 140 reg = <3>; 141 142 vin2b_ep: endpoint { 143 remote-endpoint = <&camera4>; 144 hsync-active = <1>; 145 vsync-active = <1>; 146 pclk-sample = <0>; 147 bus-width = <8>; 148 }; 149 }; 150 }; 151 }; 152... 153