xref: /linux/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/rockchip,rk3568-mipi-csi2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip MIPI CSI-2 Receiver
8
9maintainers:
10  - Michael Riesch <michael.riesch@collabora.com>
11
12description:
13  The Rockchip MIPI CSI-2 Receiver is a CSI-2 bridge with one input port and
14  one output port. It receives the data with the help of an external MIPI PHY
15  (C-PHY or D-PHY) and passes it to the Rockchip Video Capture (VICAP) block.
16
17properties:
18  compatible:
19    enum:
20      - rockchip,rk3568-mipi-csi2
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    items:
27      - description: Interrupt that signals changes in CSI2HOST_ERR1.
28      - description: Interrupt that signals changes in CSI2HOST_ERR2.
29
30  interrupt-names:
31    items:
32      - const: err1
33      - const: err2
34
35  clocks:
36    maxItems: 1
37
38  phys:
39    maxItems: 1
40    description: MIPI C-PHY or D-PHY.
41
42  ports:
43    $ref: /schemas/graph.yaml#/properties/ports
44
45    properties:
46      port@0:
47        $ref: /schemas/graph.yaml#/$defs/port-base
48        unevaluatedProperties: false
49        description: Input port node. Connect to e.g., a MIPI CSI-2 image sensor.
50
51        properties:
52          endpoint:
53            $ref: video-interfaces.yaml#
54            unevaluatedProperties: false
55
56            properties:
57              bus-type:
58                enum:
59                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
60                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
61
62              data-lanes:
63                minItems: 1
64                maxItems: 4
65
66            required:
67              - bus-type
68              - data-lanes
69
70      port@1:
71        $ref: /schemas/graph.yaml#/properties/port
72        description: Output port connected to a Rockchip VICAP port.
73
74    required:
75      - port@0
76      - port@1
77
78  power-domains:
79    maxItems: 1
80
81  resets:
82    maxItems: 1
83
84required:
85  - compatible
86  - reg
87  - clocks
88  - phys
89  - ports
90  - power-domains
91  - resets
92
93additionalProperties: false
94
95examples:
96  - |
97    #include <dt-bindings/clock/rk3568-cru.h>
98    #include <dt-bindings/interrupt-controller/arm-gic.h>
99    #include <dt-bindings/media/video-interfaces.h>
100    #include <dt-bindings/power/rk3568-power.h>
101
102    soc {
103        interrupt-parent = <&gic>;
104        #address-cells = <2>;
105        #size-cells = <2>;
106
107        csi: csi@fdfb0000 {
108            compatible = "rockchip,rk3568-mipi-csi2";
109            reg = <0x0 0xfdfb0000 0x0 0x10000>;
110            interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
111                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
112            interrupt-names = "err1", "err2";
113            clocks = <&cru PCLK_CSI2HOST1>;
114            phys = <&csi_dphy>;
115            power-domains = <&power RK3568_PD_VI>;
116            resets = <&cru SRST_P_CSI2HOST1>;
117
118            ports {
119                #address-cells = <1>;
120                #size-cells = <0>;
121
122                csi_in: port@0 {
123                    reg = <0>;
124
125                    csi_input: endpoint {
126                        bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
127                        data-lanes = <1 2 3 4>;
128                        remote-endpoint = <&imx415_output>;
129                    };
130                };
131
132                csi_out: port@1 {
133                    reg = <1>;
134
135                    csi_output: endpoint {
136                        remote-endpoint = <&vicap_mipi_input>;
137                    };
138                };
139            };
140        };
141    };
142