1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8650 Camera Subsystem (CAMSS) 8 9maintainers: 10 - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> 11 12description: 13 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. 14 15properties: 16 compatible: 17 const: qcom,sm8650-camss 18 19 reg: 20 maxItems: 17 21 22 reg-names: 23 items: 24 - const: csid_wrapper 25 - const: csid0 26 - const: csid1 27 - const: csid2 28 - const: csid_lite0 29 - const: csid_lite1 30 - const: csiphy0 31 - const: csiphy1 32 - const: csiphy2 33 - const: csiphy3 34 - const: csiphy4 35 - const: csiphy5 36 - const: vfe0 37 - const: vfe1 38 - const: vfe2 39 - const: vfe_lite0 40 - const: vfe_lite1 41 42 clocks: 43 maxItems: 33 44 45 clock-names: 46 items: 47 - const: camnoc_axi 48 - const: cpas_ahb 49 - const: cpas_fast_ahb 50 - const: cpas_vfe0 51 - const: cpas_vfe1 52 - const: cpas_vfe2 53 - const: cpas_vfe_lite 54 - const: csid 55 - const: csiphy0 56 - const: csiphy0_timer 57 - const: csiphy1 58 - const: csiphy1_timer 59 - const: csiphy2 60 - const: csiphy2_timer 61 - const: csiphy3 62 - const: csiphy3_timer 63 - const: csiphy4 64 - const: csiphy4_timer 65 - const: csiphy5 66 - const: csiphy5_timer 67 - const: csiphy_rx 68 - const: gcc_axi_hf 69 - const: qdss_debug_xo 70 - const: vfe0 71 - const: vfe0_fast_ahb 72 - const: vfe1 73 - const: vfe1_fast_ahb 74 - const: vfe2 75 - const: vfe2_fast_ahb 76 - const: vfe_lite 77 - const: vfe_lite_ahb 78 - const: vfe_lite_cphy_rx 79 - const: vfe_lite_csid 80 81 interrupts: 82 maxItems: 16 83 84 interrupt-names: 85 items: 86 - const: csid0 87 - const: csid1 88 - const: csid2 89 - const: csid_lite0 90 - const: csid_lite1 91 - const: csiphy0 92 - const: csiphy1 93 - const: csiphy2 94 - const: csiphy3 95 - const: csiphy4 96 - const: csiphy5 97 - const: vfe0 98 - const: vfe1 99 - const: vfe2 100 - const: vfe_lite0 101 - const: vfe_lite1 102 103 interconnects: 104 maxItems: 2 105 106 interconnect-names: 107 items: 108 - const: ahb 109 - const: hf_mnoc 110 111 iommus: 112 maxItems: 3 113 114 power-domains: 115 items: 116 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. 117 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. 118 - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. 119 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. 120 121 power-domain-names: 122 items: 123 - const: ife0 124 - const: ife1 125 - const: ife2 126 - const: top 127 128 ports: 129 $ref: /schemas/graph.yaml#/properties/ports 130 131 description: 132 CSI input ports. 133 134 patternProperties: 135 "^port@[0-5]$": 136 $ref: /schemas/graph.yaml#/$defs/port-base 137 unevaluatedProperties: false 138 139 description: 140 Input port for receiving CSI data from a CSIPHY. 141 142 properties: 143 endpoint: 144 $ref: video-interfaces.yaml# 145 unevaluatedProperties: false 146 147 properties: 148 data-lanes: 149 minItems: 1 150 maxItems: 4 151 152 bus-type: 153 enum: 154 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 155 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 156 157 required: 158 - data-lanes 159 160 vdd-csiphy01-0p9-supply: 161 description: 162 Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. 163 164 vdd-csiphy01-1p2-supply: 165 description: 166 Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. 167 168 vdd-csiphy24-0p9-supply: 169 description: 170 Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. 171 172 vdd-csiphy24-1p2-supply: 173 description: 174 Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. 175 176 vdd-csiphy35-0p9-supply: 177 description: 178 Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. 179 180 vdd-csiphy35-1p2-supply: 181 description: 182 Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. 183 184required: 185 - compatible 186 - reg 187 - reg-names 188 - clocks 189 - clock-names 190 - interconnects 191 - interconnect-names 192 - interrupts 193 - interrupt-names 194 - iommus 195 - power-domains 196 - power-domain-names 197 198additionalProperties: false 199 200examples: 201 - | 202 #include <dt-bindings/clock/qcom,sm8650-camcc.h> 203 #include <dt-bindings/clock/qcom,sm8650-gcc.h> 204 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 205 #include <dt-bindings/interrupt-controller/arm-gic.h> 206 207 soc { 208 #address-cells = <2>; 209 #size-cells = <2>; 210 211 isp@acb6000 { 212 compatible = "qcom,sm8650-camss"; 213 reg = <0 0x0acb6000 0 0x1000>, 214 <0 0x0acb8000 0 0x1000>, 215 <0 0x0acba000 0 0x1000>, 216 <0 0x0acbc000 0 0x1000>, 217 <0 0x0accb000 0 0x1000>, 218 <0 0x0acd0000 0 0x1000>, 219 <0 0x0ace4000 0 0x2000>, 220 <0 0x0ace6000 0 0x2000>, 221 <0 0x0ace8000 0 0x2000>, 222 <0 0x0acea000 0 0x2000>, 223 <0 0x0acec000 0 0x2000>, 224 <0 0x0acee000 0 0x2000>, 225 <0 0x0ac62000 0 0xf000>, 226 <0 0x0ac71000 0 0xf000>, 227 <0 0x0ac80000 0 0xf000>, 228 <0 0x0accc000 0 0x2000>, 229 <0 0x0acd1000 0 0x2000>; 230 reg-names = "csid_wrapper", 231 "csid0", 232 "csid1", 233 "csid2", 234 "csid_lite0", 235 "csid_lite1", 236 "csiphy0", 237 "csiphy1", 238 "csiphy2", 239 "csiphy3", 240 "csiphy4", 241 "csiphy5", 242 "vfe0", 243 "vfe1", 244 "vfe2", 245 "vfe_lite0", 246 "vfe_lite1"; 247 clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, 248 <&camcc CAM_CC_CPAS_AHB_CLK>, 249 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 250 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 251 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 252 <&camcc CAM_CC_CPAS_IFE_2_CLK>, 253 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 254 <&camcc CAM_CC_CSID_CLK>, 255 <&camcc CAM_CC_CSIPHY0_CLK>, 256 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 257 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 258 <&camcc CAM_CC_CSIPHY1_CLK>, 259 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 260 <&camcc CAM_CC_CSIPHY2_CLK>, 261 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 262 <&camcc CAM_CC_CSIPHY3_CLK>, 263 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 264 <&camcc CAM_CC_CSIPHY4_CLK>, 265 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 266 <&camcc CAM_CC_CSIPHY5_CLK>, 267 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 268 <&gcc GCC_CAMERA_HF_AXI_CLK>, 269 <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, 270 <&camcc CAM_CC_IFE_0_CLK>, 271 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 272 <&camcc CAM_CC_IFE_1_CLK>, 273 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 274 <&camcc CAM_CC_IFE_2_CLK>, 275 <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, 276 <&camcc CAM_CC_IFE_LITE_CLK>, 277 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 278 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 279 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 280 clock-names = "camnoc_axi", 281 "cpas_ahb", 282 "cpas_fast_ahb", 283 "cpas_vfe0", 284 "cpas_vfe1", 285 "cpas_vfe2", 286 "cpas_vfe_lite", 287 "csid", 288 "csiphy0", 289 "csiphy0_timer", 290 "csiphy1", 291 "csiphy1_timer", 292 "csiphy2", 293 "csiphy2_timer", 294 "csiphy3", 295 "csiphy3_timer", 296 "csiphy4", 297 "csiphy4_timer", 298 "csiphy5", 299 "csiphy5_timer", 300 "csiphy_rx", 301 "gcc_axi_hf", 302 "qdss_debug_xo", 303 "vfe0", 304 "vfe0_fast_ahb", 305 "vfe1", 306 "vfe1_fast_ahb", 307 "vfe2", 308 "vfe2_fast_ahb", 309 "vfe_lite", 310 "vfe_lite_ahb", 311 "vfe_lite_cphy_rx", 312 "vfe_lite_csid"; 313 interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; 329 interrupt-names = "csid0", 330 "csid1", 331 "csid2", 332 "csid_lite0", 333 "csid_lite1", 334 "csiphy0", 335 "csiphy1", 336 "csiphy2", 337 "csiphy3", 338 "csiphy4", 339 "csiphy5", 340 "vfe0", 341 "vfe1", 342 "vfe2", 343 "vfe_lite0", 344 "vfe_lite1"; 345 interconnects = <&gem_noc MASTER_APPSS_PROC 0 346 &config_noc SLAVE_CAMERA_CFG 0>, 347 <&mmss_noc MASTER_CAMNOC_HF 0 348 &mc_virt SLAVE_EBI1 0>; 349 interconnect-names = "ahb", "hf_mnoc"; 350 iommus = <&apps_smmu 0x800 0x20>, 351 <&apps_smmu 0x18a0 0x40>, 352 <&apps_smmu 0x1860 0x00>; 353 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 354 <&camcc CAM_CC_IFE_1_GDSC>, 355 <&camcc CAM_CC_IFE_2_GDSC>, 356 <&camcc CAM_CC_TITAN_TOP_GDSC>; 357 power-domain-names = "ife0", "ife1", "ife2", "top"; 358 vdd-csiphy01-0p9-supply = <&vreg_0p9>; 359 vdd-csiphy01-1p2-supply = <&vreg_1p2>; 360 361 ports { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 port@1 { 366 reg = <1>; 367 368 csiphy1_ep: endpoint { 369 data-lanes = <0 1>; 370 remote-endpoint = <&camera_sensor>; 371 }; 372 }; 373 }; 374 }; 375 }; 376