1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,sa8775p-camss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SA8775P CAMSS ISP 8 9maintainers: 10 - Vikram Sharma <quic_vikramsa@quicinc.com> 11 12description: 13 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. 14 15properties: 16 compatible: 17 const: qcom,sa8775p-camss 18 19 reg: 20 maxItems: 22 21 22 reg-names: 23 items: 24 - const: csid_wrapper 25 - const: csid0 26 - const: csid1 27 - const: csid_lite0 28 - const: csid_lite1 29 - const: csid_lite2 30 - const: csid_lite3 31 - const: csid_lite4 32 - const: csiphy0 33 - const: csiphy1 34 - const: csiphy2 35 - const: csiphy3 36 - const: tpg0 37 - const: tpg1 38 - const: tpg2 39 - const: vfe0 40 - const: vfe1 41 - const: vfe_lite0 42 - const: vfe_lite1 43 - const: vfe_lite2 44 - const: vfe_lite3 45 - const: vfe_lite4 46 47 clocks: 48 maxItems: 28 49 50 clock-names: 51 items: 52 - const: camnoc_axi 53 - const: core_ahb 54 - const: cpas_ahb 55 - const: cpas_fast_ahb_clk 56 - const: cpas_vfe_lite 57 - const: cpas_vfe0 58 - const: cpas_vfe1 59 - const: csid 60 - const: csiphy0 61 - const: csiphy0_timer 62 - const: csiphy1 63 - const: csiphy1_timer 64 - const: csiphy2 65 - const: csiphy2_timer 66 - const: csiphy3 67 - const: csiphy3_timer 68 - const: csiphy_rx 69 - const: gcc_axi_hf 70 - const: gcc_axi_sf 71 - const: icp_ahb 72 - const: vfe0 73 - const: vfe0_fast_ahb 74 - const: vfe1 75 - const: vfe1_fast_ahb 76 - const: vfe_lite 77 - const: vfe_lite_ahb 78 - const: vfe_lite_cphy_rx 79 - const: vfe_lite_csid 80 81 interrupts: 82 maxItems: 21 83 84 interrupt-names: 85 items: 86 - const: csid0 87 - const: csid1 88 - const: csid_lite0 89 - const: csid_lite1 90 - const: csid_lite2 91 - const: csid_lite3 92 - const: csid_lite4 93 - const: csiphy0 94 - const: csiphy1 95 - const: csiphy2 96 - const: csiphy3 97 - const: tpg0 98 - const: tpg1 99 - const: tpg2 100 - const: vfe0 101 - const: vfe1 102 - const: vfe_lite0 103 - const: vfe_lite1 104 - const: vfe_lite2 105 - const: vfe_lite3 106 - const: vfe_lite4 107 108 interconnects: 109 maxItems: 2 110 111 interconnect-names: 112 items: 113 - const: ahb 114 - const: hf_0 115 116 iommus: 117 maxItems: 1 118 119 power-domains: 120 items: 121 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. 122 123 power-domain-names: 124 items: 125 - const: top 126 127 vdda-phy-supply: 128 description: 129 Phandle to a regulator supply to PHY core block. 130 131 vdda-pll-supply: 132 description: 133 Phandle to 1.8V regulator supply to PHY refclk pll block. 134 135 ports: 136 $ref: /schemas/graph.yaml#/properties/ports 137 138 description: 139 CSI input ports. 140 141 patternProperties: 142 "^port@[0-3]+$": 143 $ref: /schemas/graph.yaml#/$defs/port-base 144 unevaluatedProperties: false 145 description: 146 Input port for receiving CSI data on CSIPHY 0-3. 147 148 properties: 149 endpoint: 150 $ref: video-interfaces.yaml# 151 unevaluatedProperties: false 152 153 properties: 154 data-lanes: 155 minItems: 1 156 maxItems: 4 157 158 required: 159 - data-lanes 160 161required: 162 - compatible 163 - reg 164 - reg-names 165 - clocks 166 - clock-names 167 - interrupts 168 - interrupt-names 169 - interconnects 170 - interconnect-names 171 - iommus 172 - power-domains 173 - power-domain-names 174 - vdda-phy-supply 175 - vdda-pll-supply 176 - ports 177 178additionalProperties: false 179 180examples: 181 - | 182 #include <dt-bindings/clock/qcom,sa8775p-camcc.h> 183 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 184 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 185 #include <dt-bindings/interconnect/qcom,icc.h> 186 #include <dt-bindings/interrupt-controller/arm-gic.h> 187 #include <dt-bindings/power/qcom-rpmpd.h> 188 189 soc { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 193 isp@ac78000 { 194 compatible = "qcom,sa8775p-camss"; 195 196 reg = <0x0 0xac78000 0x0 0x1000>, 197 <0x0 0xac7a000 0x0 0x0f00>, 198 <0x0 0xac7c000 0x0 0x0f00>, 199 <0x0 0xac84000 0x0 0x0f00>, 200 <0x0 0xac88000 0x0 0x0f00>, 201 <0x0 0xac8c000 0x0 0x0f00>, 202 <0x0 0xac90000 0x0 0x0f00>, 203 <0x0 0xac94000 0x0 0x0f00>, 204 <0x0 0xac9c000 0x0 0x2000>, 205 <0x0 0xac9e000 0x0 0x2000>, 206 <0x0 0xaca0000 0x0 0x2000>, 207 <0x0 0xaca2000 0x0 0x2000>, 208 <0x0 0xacac000 0x0 0x0400>, 209 <0x0 0xacad000 0x0 0x0400>, 210 <0x0 0xacae000 0x0 0x0400>, 211 <0x0 0xac4d000 0x0 0xd000>, 212 <0x0 0xac5a000 0x0 0xd000>, 213 <0x0 0xac85000 0x0 0x0d00>, 214 <0x0 0xac89000 0x0 0x0d00>, 215 <0x0 0xac8d000 0x0 0x0d00>, 216 <0x0 0xac91000 0x0 0x0d00>, 217 <0x0 0xac95000 0x0 0x0d00>; 218 reg-names = "csid_wrapper", 219 "csid0", 220 "csid1", 221 "csid_lite0", 222 "csid_lite1", 223 "csid_lite2", 224 "csid_lite3", 225 "csid_lite4", 226 "csiphy0", 227 "csiphy1", 228 "csiphy2", 229 "csiphy3", 230 "tpg0", 231 "tpg1", 232 "tpg2", 233 "vfe0", 234 "vfe1", 235 "vfe_lite0", 236 "vfe_lite1", 237 "vfe_lite2", 238 "vfe_lite3", 239 "vfe_lite4"; 240 241 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 242 <&camcc CAM_CC_CORE_AHB_CLK>, 243 <&camcc CAM_CC_CPAS_AHB_CLK>, 244 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 245 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 246 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 247 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 248 <&camcc CAM_CC_CSID_CLK>, 249 <&camcc CAM_CC_CSIPHY0_CLK>, 250 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 251 <&camcc CAM_CC_CSIPHY1_CLK>, 252 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 253 <&camcc CAM_CC_CSIPHY2_CLK>, 254 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 255 <&camcc CAM_CC_CSIPHY3_CLK>, 256 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 257 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 258 <&gcc GCC_CAMERA_HF_AXI_CLK>, 259 <&gcc GCC_CAMERA_SF_AXI_CLK>, 260 <&camcc CAM_CC_ICP_AHB_CLK>, 261 <&camcc CAM_CC_IFE_0_CLK>, 262 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 263 <&camcc CAM_CC_IFE_1_CLK>, 264 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 265 <&camcc CAM_CC_IFE_LITE_CLK>, 266 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 267 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 268 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 269 clock-names = "camnoc_axi", 270 "core_ahb", 271 "cpas_ahb", 272 "cpas_fast_ahb_clk", 273 "cpas_vfe_lite", 274 "cpas_vfe0", 275 "cpas_vfe1", 276 "csid", 277 "csiphy0", 278 "csiphy0_timer", 279 "csiphy1", 280 "csiphy1_timer", 281 "csiphy2", 282 "csiphy2_timer", 283 "csiphy3", 284 "csiphy3_timer", 285 "csiphy_rx", 286 "gcc_axi_hf", 287 "gcc_axi_sf", 288 "icp_ahb", 289 "vfe0", 290 "vfe0_fast_ahb", 291 "vfe1", 292 "vfe1_fast_ahb", 293 "vfe_lite", 294 "vfe_lite_ahb", 295 "vfe_lite_cphy_rx", 296 "vfe_lite_csid"; 297 298 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 301 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 302 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 303 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 307 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 319 interrupt-names = "csid0", 320 "csid1", 321 "csid_lite0", 322 "csid_lite1", 323 "csid_lite2", 324 "csid_lite3", 325 "csid_lite4", 326 "csiphy0", 327 "csiphy1", 328 "csiphy2", 329 "csiphy3", 330 "tpg0", 331 "tpg1", 332 "tpg2", 333 "vfe0", 334 "vfe1", 335 "vfe_lite0", 336 "vfe_lite1", 337 "vfe_lite2", 338 "vfe_lite3", 339 "vfe_lite4"; 340 341 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 342 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 343 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 344 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 345 interconnect-names = "ahb", 346 "hf_0"; 347 348 iommus = <&apps_smmu 0x3400 0x20>; 349 350 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 351 power-domain-names = "top"; 352 353 vdda-phy-supply = <&vreg_l4a_0p88>; 354 vdda-pll-supply = <&vreg_l1c_1p2>; 355 356 ports { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 }; 360 }; 361 }; 362