xref: /linux/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml (revision f4cdf7ca9a1fdcca413157df19753f388a5a224e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,milos-iris.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Milos SoC Iris video encoder and decoder
8
9maintainers:
10  - Alexander Koskovich <akoskovich@pm.me>
11
12description:
13  The Iris video processing unit on Qualcomm Milos SoC is a video encode and
14  decode accelerator.
15
16properties:
17  compatible:
18    enum:
19      - qcom,milos-iris
20
21  clocks:
22    maxItems: 3
23
24  clock-names:
25    items:
26      - const: iface
27      - const: core
28      - const: vcodec0_core
29
30  dma-coherent: true
31
32  interconnects:
33    maxItems: 2
34
35  interconnect-names:
36    items:
37      - const: cpu-cfg
38      - const: video-mem
39
40  iommus:
41    maxItems: 2
42
43  operating-points-v2: true
44  opp-table:
45    type: object
46
47  power-domains:
48    maxItems: 4
49
50  power-domain-names:
51    items:
52      - const: venus
53      - const: vcodec0
54      - const: cx
55      - const: mx
56
57  resets:
58    maxItems: 2
59
60  reset-names:
61    items:
62      - const: bus
63      - const: core
64
65required:
66  - compatible
67  - dma-coherent
68  - interconnects
69  - interconnect-names
70  - iommus
71  - power-domain-names
72  - resets
73  - reset-names
74
75allOf:
76  - $ref: qcom,venus-common.yaml#
77
78unevaluatedProperties: false
79
80examples:
81  - |
82    #include <dt-bindings/clock/qcom,rpmh.h>
83    #include <dt-bindings/clock/qcom,milos-gcc.h>
84    #include <dt-bindings/clock/qcom,milos-videocc.h>
85    #include <dt-bindings/interrupt-controller/arm-gic.h>
86    #include <dt-bindings/interconnect/qcom,icc.h>
87    #include <dt-bindings/interconnect/qcom,milos-rpmh.h>
88    #include <dt-bindings/power/qcom-rpmpd.h>
89    #include <dt-bindings/power/qcom,rpmhpd.h>
90
91    video-codec@aa00000 {
92        compatible = "qcom,milos-iris";
93        reg = <0x0aa00000 0xf0000>;
94
95        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
96                 <&videocc VIDEO_CC_MVS0C_CLK>,
97                 <&videocc VIDEO_CC_MVS0_CLK>;
98        clock-names = "iface",
99                      "core",
100                      "vcodec0_core";
101
102        dma-coherent;
103        iommus = <&apps_smmu 0x1960 0>,
104                 <&apps_smmu 0x1967 0>;
105
106        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
107                         &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
108                        <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
109                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
110        interconnect-names = "cpu-cfg",
111                             "video-mem";
112
113        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
114
115        operating-points-v2 = <&iris_opp_table>;
116
117        memory-region = <&video_mem>;
118
119        power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
120                        <&videocc VIDEO_CC_MVS0_GDSC>,
121                        <&rpmhpd RPMHPD_CX>,
122                        <&rpmhpd RPMHPD_MX>;
123        power-domain-names = "venus",
124                             "vcodec0",
125                             "cx",
126                             "mx";
127
128        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
129                 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
130        reset-names = "bus",
131                      "core";
132
133        iris_opp_table: opp-table {
134            compatible = "operating-points-v2";
135
136            opp-240000000 {
137                opp-hz = /bits/ 64 <240000000>;
138                required-opps = <&rpmhpd_opp_low_svs>,
139                                <&rpmhpd_opp_svs>;
140            };
141
142            opp-338000000 {
143                opp-hz = /bits/ 64 <338000000>;
144                required-opps = <&rpmhpd_opp_svs>,
145                                <&rpmhpd_opp_svs>;
146            };
147
148            opp-366000000 {
149                opp-hz = /bits/ 64 <366000000>;
150                required-opps = <&rpmhpd_opp_svs_l1>,
151                                <&rpmhpd_opp_svs>;
152            };
153
154            opp-444000000 {
155                opp-hz = /bits/ 64 <444000000>;
156                required-opps = <&rpmhpd_opp_nom>,
157                                <&rpmhpd_opp_svs_l1>;
158            };
159
160            opp-552000000 {
161                opp-hz = /bits/ 64 <552000000>;
162                required-opps = <&rpmhpd_opp_turbo>,
163                                <&rpmhpd_opp_nom>;
164            };
165        };
166    };
167