xref: /linux/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: i.MX8QM Image Sensing Interface
8
9maintainers:
10  - Frank Li <Frank.Li@nxp.com>
11
12description:
13  The Image Sensing Interface (ISI) combines image processing pipelines with
14  DMA engines to process and capture frames originating from a variety of
15  sources. The inputs to the ISI go through Pixel Link interfaces, and their
16  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
18
19properties:
20  compatible:
21    enum:
22      - fsl,imx8qm-isi
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    maxItems: 8
29
30  clock-names:
31    items:
32      - const: per0
33      - const: per1
34      - const: per2
35      - const: per3
36      - const: per4
37      - const: per5
38      - const: per6
39      - const: per7
40
41  interrupts:
42    maxItems: 8
43
44  power-domains:
45    maxItems: 8
46
47  ports:
48    $ref: /schemas/graph.yaml#/properties/ports
49    properties:
50      port@2:
51        $ref: /schemas/graph.yaml#/properties/port
52        description: MIPI CSI-2 RX 0
53      port@3:
54        $ref: /schemas/graph.yaml#/properties/port
55        description: MIPI CSI-2 RX 1
56      port@4:
57        $ref: /schemas/graph.yaml#/properties/port
58        description: HDMI RX
59
60required:
61  - compatible
62  - reg
63  - clocks
64  - clock-names
65  - interrupts
66  - power-domains
67  - ports
68
69additionalProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/interrupt-controller/arm-gic.h>
74    #include <dt-bindings/interrupt-controller/irq.h>
75    #include <dt-bindings/clock/imx8-clock.h>
76    #include <dt-bindings/clock/imx8-lpcg.h>
77    #include <dt-bindings/firmware/imx/rsrc.h>
78
79    image-controller@58100000 {
80        compatible = "fsl,imx8qm-isi";
81        reg = <0x58100000 0x80000>;
82        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
83                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
84                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
85                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
86                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
87                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
88                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
89                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
90        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
91                 <&pdma1_lpcg IMX_LPCG_CLK_0>,
92                 <&pdma2_lpcg IMX_LPCG_CLK_0>,
93                 <&pdma3_lpcg IMX_LPCG_CLK_0>,
94                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
95                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
96                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
97                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
98        clock-names = "per0", "per1", "per2", "per3",
99                      "per4", "per5", "per6", "per7";
100        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,
101                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,
102                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,
103                        <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;
104
105        ports {
106            #address-cells = <1>;
107            #size-cells = <0>;
108
109            port@2 {
110                reg = <2>;
111                endpoint {
112                    remote-endpoint = <&mipi_csi0_out>;
113                };
114            };
115        };
116    };
117...
118