xref: /linux/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml (revision 9b838a3c32d7a1edd7edeec1bc455eca76622218) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A10 Video Engine Device Tree Bindings
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - allwinner,sun4i-a10-video-engine
17      - allwinner,sun5i-a13-video-engine
18      - allwinner,sun7i-a20-video-engine
19      - allwinner,sun8i-a33-video-engine
20      - allwinner,sun8i-h3-video-engine
21      - allwinner,sun8i-v3s-video-engine
22      - allwinner,sun8i-r40-video-engine
23      - allwinner,sun50i-a64-video-engine
24      - allwinner,sun50i-h5-video-engine
25      - allwinner,sun50i-h6-video-engine
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    items:
35      - description: Bus Clock
36      - description: Module Clock
37      - description: RAM Clock
38
39  clock-names:
40    items:
41      - const: ahb
42      - const: mod
43      - const: ram
44
45  resets:
46    maxItems: 1
47
48  allwinner,sram:
49    $ref: /schemas/types.yaml#/definitions/phandle-array
50    description: Phandle to the device SRAM
51
52  iommus:
53    maxItems: 1
54
55  memory-region:
56    maxItems: 1
57    description:
58      CMA pool to use for buffers allocation instead of the default
59      CMA pool.
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - clocks
66  - clock-names
67  - resets
68  - allwinner,sram
69
70additionalProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/interrupt-controller/arm-gic.h>
75    #include <dt-bindings/clock/sun7i-a20-ccu.h>
76    #include <dt-bindings/reset/sun4i-a10-ccu.h>
77
78    video-codec@1c0e000 {
79        compatible = "allwinner,sun7i-a20-video-engine";
80        reg = <0x01c0e000 0x1000>;
81        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
82        clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
83                 <&ccu CLK_DRAM_VE>;
84        clock-names = "ahb", "mod", "ram";
85        resets = <&ccu RST_VE>;
86        allwinner,sram = <&ve_sram 1>;
87    };
88
89...
90