1*7d33dd2dSJammy Huang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*7d33dd2dSJammy Huang%YAML 1.2 3*7d33dd2dSJammy Huang--- 4*7d33dd2dSJammy Huang$id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml# 5*7d33dd2dSJammy Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7d33dd2dSJammy Huang 7*7d33dd2dSJammy Huangtitle: ASPEED AST2700 mailbox controller 8*7d33dd2dSJammy Huang 9*7d33dd2dSJammy Huangmaintainers: 10*7d33dd2dSJammy Huang - Jammy Huang <jammy_huang@aspeedtech.com> 11*7d33dd2dSJammy Huang 12*7d33dd2dSJammy Huangdescription: > 13*7d33dd2dSJammy Huang ASPEED AST2700 has multiple processors that need to communicate with each 14*7d33dd2dSJammy Huang other. The mailbox controller provides a way for these processors to send 15*7d33dd2dSJammy Huang messages to each other. It is a hardware-based inter-processor communication 16*7d33dd2dSJammy Huang mechanism that allows processors to send and receive messages through 17*7d33dd2dSJammy Huang dedicated channels. 18*7d33dd2dSJammy Huang 19*7d33dd2dSJammy Huang The mailbox's tx/rx are independent, meaning that one processor can send a 20*7d33dd2dSJammy Huang message while another processor is receiving a message simultaneously. 21*7d33dd2dSJammy Huang There are 4 channels available for both tx and rx operations. Each channel 22*7d33dd2dSJammy Huang has a FIFO buffer that can hold messages of a fixed size (32 bytes in this 23*7d33dd2dSJammy Huang case). 24*7d33dd2dSJammy Huang 25*7d33dd2dSJammy Huang The mailbox controller also supports interrupt generation, allowing 26*7d33dd2dSJammy Huang processors to notify each other when a message is available or when an event 27*7d33dd2dSJammy Huang occurs. 28*7d33dd2dSJammy Huang 29*7d33dd2dSJammy Huangproperties: 30*7d33dd2dSJammy Huang compatible: 31*7d33dd2dSJammy Huang const: aspeed,ast2700-mailbox 32*7d33dd2dSJammy Huang 33*7d33dd2dSJammy Huang reg: 34*7d33dd2dSJammy Huang items: 35*7d33dd2dSJammy Huang - description: TX control register 36*7d33dd2dSJammy Huang - description: RX control register 37*7d33dd2dSJammy Huang 38*7d33dd2dSJammy Huang reg-names: 39*7d33dd2dSJammy Huang items: 40*7d33dd2dSJammy Huang - const: tx 41*7d33dd2dSJammy Huang - const: rx 42*7d33dd2dSJammy Huang 43*7d33dd2dSJammy Huang interrupts: 44*7d33dd2dSJammy Huang maxItems: 1 45*7d33dd2dSJammy Huang 46*7d33dd2dSJammy Huang "#mbox-cells": 47*7d33dd2dSJammy Huang const: 1 48*7d33dd2dSJammy Huang 49*7d33dd2dSJammy Huangrequired: 50*7d33dd2dSJammy Huang - compatible 51*7d33dd2dSJammy Huang - reg 52*7d33dd2dSJammy Huang - reg-names 53*7d33dd2dSJammy Huang - interrupts 54*7d33dd2dSJammy Huang - "#mbox-cells" 55*7d33dd2dSJammy Huang 56*7d33dd2dSJammy HuangadditionalProperties: false 57*7d33dd2dSJammy Huang 58*7d33dd2dSJammy Huangexamples: 59*7d33dd2dSJammy Huang - | 60*7d33dd2dSJammy Huang #include <dt-bindings/interrupt-controller/arm-gic.h> 61*7d33dd2dSJammy Huang 62*7d33dd2dSJammy Huang mailbox@12c1c200 { 63*7d33dd2dSJammy Huang compatible = "aspeed,ast2700-mailbox"; 64*7d33dd2dSJammy Huang reg = <0x12c1c200 0x100>, <0x12c1c300 0x100>; 65*7d33dd2dSJammy Huang reg-names = "tx", "rx"; 66*7d33dd2dSJammy Huang interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 67*7d33dd2dSJammy Huang #mbox-cells = <1>; 68*7d33dd2dSJammy Huang }; 69