xref: /linux/Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml (revision 4994ef0fe01e0c58a9af187f98a030c35dfb1a93) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/ti,omap-iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: OMAP2+ IOMMU
8
9maintainers:
10  - Bhargav Joshi <j.bhargav.u@gmail.com>
11
12properties:
13  compatible:
14    enum:
15      - ti,omap2-iommu
16      - ti,omap4-iommu
17      - ti,dra7-dsp-iommu
18      - ti,dra7-iommu
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  '#iommu-cells':
27    const: 0
28
29  ti,#tlb-entries:
30    description: Number of entries in the translation look-aside buffer.
31    $ref: /schemas/types.yaml#/definitions/uint32
32    enum: [8, 32]
33    default: 32
34
35  ti,iommu-bus-err-back:
36    description:
37      Indicates the IOMMU instance supports throwing back a bus error response
38      on MMU faults.
39    type: boolean
40
41  ti,syscon-mmuconfig:
42    description:
43      Pair of the phandle to the DSP_SYSTEM syscon node that
44      contains the additional control register for enabling the MMU, and the
45      MMU instance number (0-indexed) within the sub-system. The instance number
46      should be 0 for DSP MDMA MMUs and 1 for DSP EDMA MMUs.
47    $ref: /schemas/types.yaml#/definitions/phandle-array
48    maxItems: 1
49    items:
50      items:
51        - description: phandle to the DSP_SYSTEM syscon node
52        - description: MMU instance number
53          enum: [0, 1]
54
55  ti,hwmods:
56    description: Name of the hwmod associated with the IOMMU instance
57    $ref: /schemas/types.yaml#/definitions/string
58    deprecated: true
59
60required:
61  - compatible
62  - reg
63  - '#iommu-cells'
64  - interrupts
65
66allOf:
67  - if:
68      properties:
69        compatible:
70          contains:
71            const: ti,dra7-dsp-iommu
72    then:
73      required:
74        - ti,syscon-mmuconfig
75    else:
76      properties:
77        ti,syscon-mmuconfig: false
78
79additionalProperties: false
80
81examples:
82  - |
83    mmu@480bd400 {
84        #iommu-cells = <0>;
85        compatible = "ti,omap2-iommu";
86        reg = <0x480bd400 0x80>;
87        interrupts = <24>;
88        ti,hwmods = "mmu_isp";
89        ti,#tlb-entries = <8>;
90    };
91
92  - |
93    #include <dt-bindings/interrupt-controller/arm-gic.h>
94
95    mmu@41501000 {
96        compatible = "ti,dra7-dsp-iommu";
97        reg = <0x41501000 0x100>;
98        interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
99        ti,hwmods = "mmu0_dsp2";
100        #iommu-cells = <0>;
101        ti,syscon-mmuconfig = <&dsp2_system 0x0>;
102    };
103
104  - |
105    #include <dt-bindings/interrupt-controller/arm-gic.h>
106
107    mmu@41502000 {
108        compatible = "ti,dra7-dsp-iommu";
109        reg = <0x41502000 0x100>;
110        interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
111        ti,hwmods = "mmu1_dsp2";
112        #iommu-cells = <0>;
113        ti,syscon-mmuconfig = <&dsp2_system 0x1>;
114    };
115