1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/qcom,tbu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm TBU (Translation Buffer Unit) 8 9maintainers: 10 - Georgi Djakov <quic_c_gdjako@quicinc.com> 11 12description: 13 The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains 14 a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides 15 debug features to trace and trigger debug transactions. There are multiple TBU 16 instances with each client core. 17 18properties: 19 compatible: 20 enum: 21 - qcom,sc7280-tbu 22 - qcom,sdm845-tbu 23 24 reg: 25 maxItems: 1 26 27 clocks: 28 maxItems: 1 29 30 interconnects: 31 maxItems: 1 32 33 power-domains: 34 maxItems: 1 35 36 qcom,stream-id-range: 37 description: | 38 Phandle of a SMMU device and Stream ID range (address and size) that 39 is assigned by the TBU 40 $ref: /schemas/types.yaml#/definitions/phandle-array 41 items: 42 - items: 43 - description: phandle of a smmu node 44 - description: stream id base address 45 - description: stream id size 46 47required: 48 - compatible 49 - reg 50 - qcom,stream-id-range 51 52additionalProperties: false 53 54examples: 55 - | 56 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 57 #include <dt-bindings/interconnect/qcom,icc.h> 58 #include <dt-bindings/interconnect/qcom,sdm845.h> 59 60 tbu@150e1000 { 61 compatible = "qcom,sdm845-tbu"; 62 reg = <0x150e1000 0x1000>; 63 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 64 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY 65 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 66 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; 67 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 68 }; 69... 70