1*7ce3c271SMichal Simek# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*7ce3c271SMichal Simek%YAML 1.2 3*7ce3c271SMichal Simek--- 4*7ce3c271SMichal Simek$id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml# 5*7ce3c271SMichal Simek$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7ce3c271SMichal Simek 7*7ce3c271SMichal Simektitle: Xilinx Interrupt Controller 8*7ce3c271SMichal Simek 9*7ce3c271SMichal Simekmaintainers: 10*7ce3c271SMichal Simek - Michal Simek <michal.simek@amd.com> 11*7ce3c271SMichal Simek 12*7ce3c271SMichal Simekdescription: 13*7ce3c271SMichal Simek The controller is a soft IP core that is configured at build time for the 14*7ce3c271SMichal Simek number of interrupts and the type of each interrupt. These details cannot 15*7ce3c271SMichal Simek be changed at run time. 16*7ce3c271SMichal Simek 17*7ce3c271SMichal Simekproperties: 18*7ce3c271SMichal Simek compatible: 19*7ce3c271SMichal Simek const: xlnx,xps-intc-1.00.a 20*7ce3c271SMichal Simek 21*7ce3c271SMichal Simek reg: 22*7ce3c271SMichal Simek maxItems: 1 23*7ce3c271SMichal Simek 24*7ce3c271SMichal Simek clocks: 25*7ce3c271SMichal Simek maxItems: 1 26*7ce3c271SMichal Simek 27*7ce3c271SMichal Simek power-domains: 28*7ce3c271SMichal Simek maxItems: 1 29*7ce3c271SMichal Simek 30*7ce3c271SMichal Simek resets: 31*7ce3c271SMichal Simek maxItems: 1 32*7ce3c271SMichal Simek 33*7ce3c271SMichal Simek "#interrupt-cells": 34*7ce3c271SMichal Simek const: 2 35*7ce3c271SMichal Simek description: 36*7ce3c271SMichal Simek Specifies the number of cells needed to encode an interrupt source. 37*7ce3c271SMichal Simek The value shall be a minimum of 1. The Xilinx device trees typically 38*7ce3c271SMichal Simek use 2 but the 2nd value is not used. 39*7ce3c271SMichal Simek 40*7ce3c271SMichal Simek interrupt-controller: true 41*7ce3c271SMichal Simek 42*7ce3c271SMichal Simek interrupts: 43*7ce3c271SMichal Simek maxItems: 1 44*7ce3c271SMichal Simek description: 45*7ce3c271SMichal Simek Specifies the interrupt of the parent controller from which it is chained. 46*7ce3c271SMichal Simek 47*7ce3c271SMichal Simek xlnx,kind-of-intr: 48*7ce3c271SMichal Simek $ref: /schemas/types.yaml#/definitions/uint32 49*7ce3c271SMichal Simek description: 50*7ce3c271SMichal Simek A 32 bit value specifying the interrupt type for each possible interrupt 51*7ce3c271SMichal Simek (1 = edge, 0 = level). The interrupt type typically comes in thru 52*7ce3c271SMichal Simek the device tree node of the interrupt generating device, but in this case 53*7ce3c271SMichal Simek the interrupt type is determined by the interrupt controller based on how 54*7ce3c271SMichal Simek it was implemented. 55*7ce3c271SMichal Simek 56*7ce3c271SMichal Simek xlnx,num-intr-inputs: 57*7ce3c271SMichal Simek $ref: /schemas/types.yaml#/definitions/uint32 58*7ce3c271SMichal Simek minimum: 1 59*7ce3c271SMichal Simek maximum: 32 60*7ce3c271SMichal Simek description: 61*7ce3c271SMichal Simek Specifies the number of interrupts supported by the specific 62*7ce3c271SMichal Simek implementation of the controller. 63*7ce3c271SMichal Simek 64*7ce3c271SMichal Simekrequired: 65*7ce3c271SMichal Simek - reg 66*7ce3c271SMichal Simek - "#interrupt-cells" 67*7ce3c271SMichal Simek - interrupt-controller 68*7ce3c271SMichal Simek - xlnx,kind-of-intr 69*7ce3c271SMichal Simek - xlnx,num-intr-inputs 70*7ce3c271SMichal Simek 71*7ce3c271SMichal SimekadditionalProperties: false 72*7ce3c271SMichal Simek 73*7ce3c271SMichal Simekexamples: 74*7ce3c271SMichal Simek - | 75*7ce3c271SMichal Simek interrupt-controller@41800000 { 76*7ce3c271SMichal Simek compatible = "xlnx,xps-intc-1.00.a"; 77*7ce3c271SMichal Simek reg = <0x41800000 0x10000>; 78*7ce3c271SMichal Simek #interrupt-cells = <2>; 79*7ce3c271SMichal Simek interrupt-controller; 80*7ce3c271SMichal Simek xlnx,kind-of-intr = <0x1>; 81*7ce3c271SMichal Simek xlnx,num-intr-inputs = <1>; 82*7ce3c271SMichal Simek }; 83