xref: /linux/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml (revision 0eaed89c18aeedf0898baf2dbf5ff027c6795152)
1*b417b241SBhargav Joshi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*b417b241SBhargav Joshi%YAML 1.2
3*b417b241SBhargav Joshi---
4*b417b241SBhargav Joshi$id: http://devicetree.org/schemas/interrupt-controller/ti,irq-crossbar.yaml#
5*b417b241SBhargav Joshi$schema: http://devicetree.org/meta-schemas/core.yaml#
6*b417b241SBhargav Joshi
7*b417b241SBhargav Joshititle: Texas Instruments IRQ Crossbar
8*b417b241SBhargav Joshi
9*b417b241SBhargav Joshimaintainers:
10*b417b241SBhargav Joshi  - Sricharan R <r.sricharan@ti.com>
11*b417b241SBhargav Joshi
12*b417b241SBhargav Joshidescription:
13*b417b241SBhargav Joshi  Some socs have a large number of interrupts requests to service the needs of
14*b417b241SBhargav Joshi  its many peripherals and subsystems. All of the interrupt lines from the
15*b417b241SBhargav Joshi  subsystems are not needed at the same time, so they have to be muxed to the
16*b417b241SBhargav Joshi  irq-controller appropriately. In such places a interrupt controllers are
17*b417b241SBhargav Joshi  preceded by an CROSSBAR that provides flexibility in muxing the device
18*b417b241SBhargav Joshi  requests to the controller inputs.
19*b417b241SBhargav Joshi
20*b417b241SBhargav Joshiproperties:
21*b417b241SBhargav Joshi  compatible:
22*b417b241SBhargav Joshi    const: ti,irq-crossbar
23*b417b241SBhargav Joshi
24*b417b241SBhargav Joshi  reg:
25*b417b241SBhargav Joshi    maxItems: 1
26*b417b241SBhargav Joshi
27*b417b241SBhargav Joshi  interrupt-controller: true
28*b417b241SBhargav Joshi
29*b417b241SBhargav Joshi  '#interrupt-cells':
30*b417b241SBhargav Joshi    const: 3
31*b417b241SBhargav Joshi
32*b417b241SBhargav Joshi  ti,max-irqs:
33*b417b241SBhargav Joshi    $ref: /schemas/types.yaml#/definitions/uint32
34*b417b241SBhargav Joshi    description:
35*b417b241SBhargav Joshi      Total number of irqs available at the parent interrupt controller.
36*b417b241SBhargav Joshi    minimum: 1
37*b417b241SBhargav Joshi
38*b417b241SBhargav Joshi  ti,max-crossbar-sources:
39*b417b241SBhargav Joshi    $ref: /schemas/types.yaml#/definitions/uint32
40*b417b241SBhargav Joshi    description:
41*b417b241SBhargav Joshi      Maximum number of crossbar sources that can be routed.
42*b417b241SBhargav Joshi    minimum: 1
43*b417b241SBhargav Joshi
44*b417b241SBhargav Joshi  ti,reg-size:
45*b417b241SBhargav Joshi    $ref: /schemas/types.yaml#/definitions/uint32
46*b417b241SBhargav Joshi    description:
47*b417b241SBhargav Joshi      Size of a individual register in bytes. Every individual
48*b417b241SBhargav Joshi      register is assumed to be of same size.
49*b417b241SBhargav Joshi    enum: [1, 2, 4]
50*b417b241SBhargav Joshi
51*b417b241SBhargav Joshi  ti,irqs-reserved:
52*b417b241SBhargav Joshi    $ref: /schemas/types.yaml#/definitions/uint32-array
53*b417b241SBhargav Joshi    description:
54*b417b241SBhargav Joshi      List of the reserved irq lines that are not muxed using crossbar. These
55*b417b241SBhargav Joshi      interrupt lines are reserved in the soc, so crossbar bar driver should not
56*b417b241SBhargav Joshi      consider them as free lines.
57*b417b241SBhargav Joshi
58*b417b241SBhargav Joshi  ti,irqs-skip:
59*b417b241SBhargav Joshi    $ref: /schemas/types.yaml#/definitions/uint32-array
60*b417b241SBhargav Joshi    description:
61*b417b241SBhargav Joshi      Similar to "ti,irqs-reserved", but these are for SOC-specific hard-wiring
62*b417b241SBhargav Joshi      of those irqs which unexpectedly bypasses the crossbar. These irqs have a
63*b417b241SBhargav Joshi      crossbar register, but still cannot be used.
64*b417b241SBhargav Joshi
65*b417b241SBhargav Joshi  ti,irqs-safe-map:
66*b417b241SBhargav Joshi    $ref: /schemas/types.yaml#/definitions/uint32
67*b417b241SBhargav Joshi    description:
68*b417b241SBhargav Joshi      integer which maps to a safe configuration to use when the interrupt
69*b417b241SBhargav Joshi      controller irq is unused.
70*b417b241SBhargav Joshi    default: 0
71*b417b241SBhargav Joshi
72*b417b241SBhargav Joshirequired:
73*b417b241SBhargav Joshi  - compatible
74*b417b241SBhargav Joshi  - reg
75*b417b241SBhargav Joshi  - interrupt-controller
76*b417b241SBhargav Joshi  - '#interrupt-cells'
77*b417b241SBhargav Joshi  - ti,max-irqs
78*b417b241SBhargav Joshi  - ti,max-crossbar-sources
79*b417b241SBhargav Joshi  - ti,reg-size
80*b417b241SBhargav Joshi  - ti,irqs-reserved
81*b417b241SBhargav Joshi
82*b417b241SBhargav JoshiadditionalProperties: false
83*b417b241SBhargav Joshi
84*b417b241SBhargav Joshiexamples:
85*b417b241SBhargav Joshi  - |
86*b417b241SBhargav Joshi    crossbar@4a002a48 {
87*b417b241SBhargav Joshi        compatible = "ti,irq-crossbar";
88*b417b241SBhargav Joshi        reg = <0x4a002a48 0x130>;
89*b417b241SBhargav Joshi        interrupt-controller;
90*b417b241SBhargav Joshi        #interrupt-cells = <3>;
91*b417b241SBhargav Joshi        ti,max-irqs = <160>;
92*b417b241SBhargav Joshi        ti,max-crossbar-sources = <400>;
93*b417b241SBhargav Joshi        ti,reg-size = <2>;
94*b417b241SBhargav Joshi        ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
95*b417b241SBhargav Joshi        ti,irqs-skip = <10 133 139 140>;
96*b417b241SBhargav Joshi    };
97