1*3e6cf384SAnup Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*3e6cf384SAnup Patel%YAML 1.2 3*3e6cf384SAnup Patel--- 4*3e6cf384SAnup Patel$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-system-msi.yaml# 5*3e6cf384SAnup Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6*3e6cf384SAnup Patel 7*3e6cf384SAnup Pateltitle: RISC-V RPMI system MSI service group based interrupt controller 8*3e6cf384SAnup Patel 9*3e6cf384SAnup Patelmaintainers: 10*3e6cf384SAnup Patel - Anup Patel <anup@brainfault.org> 11*3e6cf384SAnup Patel 12*3e6cf384SAnup Pateldescription: | 13*3e6cf384SAnup Patel The RISC-V Platform Management Interface (RPMI) [1] defines a 14*3e6cf384SAnup Patel messaging protocol which is modular and extensible. The supervisor 15*3e6cf384SAnup Patel software can send/receive RPMI messages via SBI MPXY extension [2] 16*3e6cf384SAnup Patel or some dedicated supervisor-mode RPMI transport. 17*3e6cf384SAnup Patel 18*3e6cf384SAnup Patel The RPMI specification [1] defines system MSI service group which 19*3e6cf384SAnup Patel allow application processors to receive MSIs upon system events 20*3e6cf384SAnup Patel such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug 21*3e6cf384SAnup Patel event, memory hotplug event, etc from the platform microcontroller. 22*3e6cf384SAnup Patel The supervisor software can access RPMI system MSI service group via 23*3e6cf384SAnup Patel SBI MPXY channel or some dedicated supervisor-mode RPMI transport. 24*3e6cf384SAnup Patel 25*3e6cf384SAnup Patel =========================================== 26*3e6cf384SAnup Patel References 27*3e6cf384SAnup Patel =========================================== 28*3e6cf384SAnup Patel 29*3e6cf384SAnup Patel [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) 30*3e6cf384SAnup Patel https://github.com/riscv-non-isa/riscv-rpmi/releases 31*3e6cf384SAnup Patel 32*3e6cf384SAnup Patel [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) 33*3e6cf384SAnup Patel https://github.com/riscv-non-isa/riscv-sbi-doc/releases 34*3e6cf384SAnup Patel 35*3e6cf384SAnup PatelallOf: 36*3e6cf384SAnup Patel - $ref: /schemas/interrupt-controller.yaml# 37*3e6cf384SAnup Patel 38*3e6cf384SAnup Patelproperties: 39*3e6cf384SAnup Patel compatible: 40*3e6cf384SAnup Patel description: 41*3e6cf384SAnup Patel Intended for use by the supervisor software. 42*3e6cf384SAnup Patel const: riscv,rpmi-system-msi 43*3e6cf384SAnup Patel 44*3e6cf384SAnup Patel mboxes: 45*3e6cf384SAnup Patel maxItems: 1 46*3e6cf384SAnup Patel description: 47*3e6cf384SAnup Patel Mailbox channel of the underlying RPMI transport or SBI message proxy channel. 48*3e6cf384SAnup Patel 49*3e6cf384SAnup Patel msi-parent: true 50*3e6cf384SAnup Patel 51*3e6cf384SAnup Patel interrupt-controller: true 52*3e6cf384SAnup Patel 53*3e6cf384SAnup Patel "#interrupt-cells": 54*3e6cf384SAnup Patel const: 1 55*3e6cf384SAnup Patel 56*3e6cf384SAnup Patelrequired: 57*3e6cf384SAnup Patel - compatible 58*3e6cf384SAnup Patel - mboxes 59*3e6cf384SAnup Patel - msi-parent 60*3e6cf384SAnup Patel - interrupt-controller 61*3e6cf384SAnup Patel - "#interrupt-cells" 62*3e6cf384SAnup Patel 63*3e6cf384SAnup PateladditionalProperties: false 64*3e6cf384SAnup Patel 65*3e6cf384SAnup Patelexamples: 66*3e6cf384SAnup Patel - | 67*3e6cf384SAnup Patel interrupt-controller { 68*3e6cf384SAnup Patel compatible = "riscv,rpmi-system-msi"; 69*3e6cf384SAnup Patel mboxes = <&mpxy_mbox 0x2000 0x0>; 70*3e6cf384SAnup Patel msi-parent = <&imsic_slevel>; 71*3e6cf384SAnup Patel interrupt-controller; 72*3e6cf384SAnup Patel #interrupt-cells = <1>; 73*3e6cf384SAnup Patel }; 74*3e6cf384SAnup Patel... 75