xref: /linux/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1)
1*c4cd2aa6SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*c4cd2aa6SRob Herring (Arm)%YAML 1.2
3*c4cd2aa6SRob Herring (Arm)---
4*c4cd2aa6SRob Herring (Arm)$id: http://devicetree.org/schemas/interrupt-controller/nvidia,tegra20-ictlr.yaml#
5*c4cd2aa6SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml#
6*c4cd2aa6SRob Herring (Arm)
7*c4cd2aa6SRob Herring (Arm)title: NVIDIA Tegra20 Legacy Interrupt Controller
8*c4cd2aa6SRob Herring (Arm)
9*c4cd2aa6SRob Herring (Arm)maintainers:
10*c4cd2aa6SRob Herring (Arm)  - Thierry Reding <treding@nvidia.com>
11*c4cd2aa6SRob Herring (Arm)  - Jonathan Hunter <jonathanh@nvidia.com>
12*c4cd2aa6SRob Herring (Arm)
13*c4cd2aa6SRob Herring (Arm)description: >
14*c4cd2aa6SRob Herring (Arm)  All Tegra SoCs contain a legacy interrupt controller that routes interrupts to
15*c4cd2aa6SRob Herring (Arm)  the GIC, and also serves as a wakeup source. It is also referred to as
16*c4cd2aa6SRob Herring (Arm)  "ictlr", hence the name of the binding.
17*c4cd2aa6SRob Herring (Arm)
18*c4cd2aa6SRob Herring (Arm)  The HW block exposes a number of interrupt controllers, each implementing a
19*c4cd2aa6SRob Herring (Arm)  set of 32 interrupts.
20*c4cd2aa6SRob Herring (Arm)
21*c4cd2aa6SRob Herring (Arm)  Notes:
22*c4cd2aa6SRob Herring (Arm)    - Because this HW ultimately routes interrupts to the GIC, the
23*c4cd2aa6SRob Herring (Arm)      interrupt specifier must be that of the GIC.
24*c4cd2aa6SRob Herring (Arm)    - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
25*c4cd2aa6SRob Herring (Arm)      are explicitly forbidden.
26*c4cd2aa6SRob Herring (Arm)
27*c4cd2aa6SRob Herring (Arm)properties:
28*c4cd2aa6SRob Herring (Arm)  compatible:
29*c4cd2aa6SRob Herring (Arm)    oneOf:
30*c4cd2aa6SRob Herring (Arm)      - items:
31*c4cd2aa6SRob Herring (Arm)          - enum:
32*c4cd2aa6SRob Herring (Arm)              - nvidia,tegra114-ictlr
33*c4cd2aa6SRob Herring (Arm)              - nvidia,tegra124-ictlr
34*c4cd2aa6SRob Herring (Arm)          - const: nvidia,tegra30-ictlr
35*c4cd2aa6SRob Herring (Arm)      - enum:
36*c4cd2aa6SRob Herring (Arm)          - nvidia,tegra20-ictlr
37*c4cd2aa6SRob Herring (Arm)          - nvidia,tegra30-ictlr
38*c4cd2aa6SRob Herring (Arm)
39*c4cd2aa6SRob Herring (Arm)  reg:
40*c4cd2aa6SRob Herring (Arm)    description: Each entry is a block of 32 interrupts
41*c4cd2aa6SRob Herring (Arm)    minItems: 4
42*c4cd2aa6SRob Herring (Arm)    maxItems: 5
43*c4cd2aa6SRob Herring (Arm)
44*c4cd2aa6SRob Herring (Arm)  interrupt-controller: true
45*c4cd2aa6SRob Herring (Arm)
46*c4cd2aa6SRob Herring (Arm)  '#interrupt-cells':
47*c4cd2aa6SRob Herring (Arm)    const: 3
48*c4cd2aa6SRob Herring (Arm)
49*c4cd2aa6SRob Herring (Arm)required:
50*c4cd2aa6SRob Herring (Arm)  - compatible
51*c4cd2aa6SRob Herring (Arm)  - reg
52*c4cd2aa6SRob Herring (Arm)  - interrupt-controller
53*c4cd2aa6SRob Herring (Arm)  - '#interrupt-cells'
54*c4cd2aa6SRob Herring (Arm)
55*c4cd2aa6SRob Herring (Arm)additionalProperties: false
56*c4cd2aa6SRob Herring (Arm)
57*c4cd2aa6SRob Herring (Arm)allOf:
58*c4cd2aa6SRob Herring (Arm)  - if:
59*c4cd2aa6SRob Herring (Arm)      properties:
60*c4cd2aa6SRob Herring (Arm)        compatible:
61*c4cd2aa6SRob Herring (Arm)          contains:
62*c4cd2aa6SRob Herring (Arm)            const: nvidia,tegra20-ictlr
63*c4cd2aa6SRob Herring (Arm)    then:
64*c4cd2aa6SRob Herring (Arm)      properties:
65*c4cd2aa6SRob Herring (Arm)        reg:
66*c4cd2aa6SRob Herring (Arm)          maxItems: 4
67*c4cd2aa6SRob Herring (Arm)    else:
68*c4cd2aa6SRob Herring (Arm)      properties:
69*c4cd2aa6SRob Herring (Arm)        reg:
70*c4cd2aa6SRob Herring (Arm)          minItems: 5
71*c4cd2aa6SRob Herring (Arm)
72*c4cd2aa6SRob Herring (Arm)examples:
73*c4cd2aa6SRob Herring (Arm)  - |
74*c4cd2aa6SRob Herring (Arm)    interrupt-controller@60004000 {
75*c4cd2aa6SRob Herring (Arm)        compatible = "nvidia,tegra20-ictlr";
76*c4cd2aa6SRob Herring (Arm)        reg = <0x60004000 64>,
77*c4cd2aa6SRob Herring (Arm)              <0x60004100 64>,
78*c4cd2aa6SRob Herring (Arm)              <0x60004200 64>,
79*c4cd2aa6SRob Herring (Arm)              <0x60004300 64>;
80*c4cd2aa6SRob Herring (Arm)        interrupt-controller;
81*c4cd2aa6SRob Herring (Arm)        #interrupt-cells = <3>;
82*c4cd2aa6SRob Herring (Arm)    };
83