xref: /linux/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/nvidia,tegra20-ictlr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra20 Legacy Interrupt Controller
8
9maintainers:
10  - Thierry Reding <treding@nvidia.com>
11  - Jonathan Hunter <jonathanh@nvidia.com>
12
13description: >
14  All Tegra SoCs contain a legacy interrupt controller that routes interrupts to
15  the GIC, and also serves as a wakeup source. It is also referred to as
16  "ictlr", hence the name of the binding.
17
18  The HW block exposes a number of interrupt controllers, each implementing a
19  set of 32 interrupts.
20
21  Notes:
22    - Because this HW ultimately routes interrupts to the GIC, the
23      interrupt specifier must be that of the GIC.
24    - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
25      are explicitly forbidden.
26
27properties:
28  compatible:
29    oneOf:
30      - items:
31          - enum:
32              - nvidia,tegra114-ictlr
33              - nvidia,tegra124-ictlr
34          - const: nvidia,tegra30-ictlr
35      - enum:
36          - nvidia,tegra20-ictlr
37          - nvidia,tegra30-ictlr
38
39  reg:
40    description: Each entry is a block of 32 interrupts
41    minItems: 4
42    maxItems: 5
43
44  interrupt-controller: true
45
46  '#interrupt-cells':
47    const: 3
48
49required:
50  - compatible
51  - reg
52  - interrupt-controller
53  - '#interrupt-cells'
54
55additionalProperties: false
56
57allOf:
58  - if:
59      properties:
60        compatible:
61          contains:
62            const: nvidia,tegra20-ictlr
63    then:
64      properties:
65        reg:
66          maxItems: 4
67    else:
68      properties:
69        reg:
70          minItems: 5
71
72examples:
73  - |
74    interrupt-controller@60004000 {
75        compatible = "nvidia,tegra20-ictlr";
76        reg = <0x60004000 64>,
77              <0x60004100 64>,
78              <0x60004200 64>,
79              <0x60004300 64>;
80        interrupt-controller;
81        #interrupt-cells = <3>;
82    };
83