1*b1ae6881SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b1ae6881SRob Herring (Arm)%YAML 1.2 3*b1ae6881SRob Herring (Arm)--- 4*b1ae6881SRob Herring (Arm)$id: http://devicetree.org/schemas/interrupt-controller/microchip,pic32mzda-evic.yaml# 5*b1ae6881SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b1ae6881SRob Herring (Arm) 7*b1ae6881SRob Herring (Arm)title: Microchip PIC32 EVIC Interrupt Controller 8*b1ae6881SRob Herring (Arm) 9*b1ae6881SRob Herring (Arm)maintainers: 10*b1ae6881SRob Herring (Arm) - Cristian Birsan <cristian.birsan@microchip.com> 11*b1ae6881SRob Herring (Arm) 12*b1ae6881SRob Herring (Arm)description: > 13*b1ae6881SRob Herring (Arm) The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). 14*b1ae6881SRob Herring (Arm) It handles all internal and external interrupts. This controller exists 15*b1ae6881SRob Herring (Arm) outside of the CPU and is the arbitrator of all interrupts (including 16*b1ae6881SRob Herring (Arm) interrupts from the CPU itself) before they are presented to the CPU. 17*b1ae6881SRob Herring (Arm) 18*b1ae6881SRob Herring (Arm) External interrupts have a software configurable edge polarity. Non external 19*b1ae6881SRob Herring (Arm) interrupts have a type and polarity that is determined by the source of the 20*b1ae6881SRob Herring (Arm) interrupt. 21*b1ae6881SRob Herring (Arm) 22*b1ae6881SRob Herring (Arm)properties: 23*b1ae6881SRob Herring (Arm) compatible: 24*b1ae6881SRob Herring (Arm) items: 25*b1ae6881SRob Herring (Arm) - const: microchip,pic32mzda-evic 26*b1ae6881SRob Herring (Arm) 27*b1ae6881SRob Herring (Arm) reg: 28*b1ae6881SRob Herring (Arm) maxItems: 1 29*b1ae6881SRob Herring (Arm) 30*b1ae6881SRob Herring (Arm) interrupt-controller: true 31*b1ae6881SRob Herring (Arm) 32*b1ae6881SRob Herring (Arm) '#interrupt-cells': 33*b1ae6881SRob Herring (Arm) const: 2 34*b1ae6881SRob Herring (Arm) 35*b1ae6881SRob Herring (Arm) interrupts: 36*b1ae6881SRob Herring (Arm) maxItems: 1 37*b1ae6881SRob Herring (Arm) 38*b1ae6881SRob Herring (Arm) microchip,external-irqs: 39*b1ae6881SRob Herring (Arm) description: 40*b1ae6881SRob Herring (Arm) External interrupts with software polarity configuration corresponding to 41*b1ae6881SRob Herring (Arm) the INTCON SFR bits. 42*b1ae6881SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32-array 43*b1ae6881SRob Herring (Arm) 44*b1ae6881SRob Herring (Arm)required: 45*b1ae6881SRob Herring (Arm) - compatible 46*b1ae6881SRob Herring (Arm) - reg 47*b1ae6881SRob Herring (Arm) - interrupt-controller 48*b1ae6881SRob Herring (Arm) - '#interrupt-cells' 49*b1ae6881SRob Herring (Arm) 50*b1ae6881SRob Herring (Arm)additionalProperties: false 51*b1ae6881SRob Herring (Arm) 52*b1ae6881SRob Herring (Arm)examples: 53*b1ae6881SRob Herring (Arm) - | 54*b1ae6881SRob Herring (Arm) interrupt-controller@1f810000 { 55*b1ae6881SRob Herring (Arm) compatible = "microchip,pic32mzda-evic"; 56*b1ae6881SRob Herring (Arm) reg = <0x1f810000 0x1000>; 57*b1ae6881SRob Herring (Arm) interrupt-controller; 58*b1ae6881SRob Herring (Arm) #interrupt-cells = <2>; 59*b1ae6881SRob Herring (Arm) microchip,external-irqs = <3 8 13 18 23>; 60*b1ae6881SRob Herring (Arm) }; 61