xref: /linux/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml (revision bf373e4c786bfe989e637195252698f45b157a68) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/microchip,pic32mzda-evic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PIC32 EVIC Interrupt Controller
8
9maintainers:
10  - Cristian Birsan <cristian.birsan@microchip.com>
11
12description: >
13  The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
14  It handles all internal and external interrupts. This controller exists
15  outside of the CPU and is the arbitrator of all interrupts (including
16  interrupts from the CPU itself) before they are presented to the CPU.
17
18  External interrupts have a software configurable edge polarity. Non external
19  interrupts have a type and polarity that is determined by the source of the
20  interrupt.
21
22properties:
23  compatible:
24    items:
25      - const: microchip,pic32mzda-evic
26
27  reg:
28    maxItems: 1
29
30  interrupt-controller: true
31
32  '#interrupt-cells':
33    const: 2
34
35  interrupts:
36    maxItems: 1
37
38  microchip,external-irqs:
39    description:
40      External interrupts with software polarity configuration corresponding to
41      the INTCON SFR bits.
42    $ref: /schemas/types.yaml#/definitions/uint32-array
43
44required:
45  - compatible
46  - reg
47  - interrupt-controller
48  - '#interrupt-cells'
49
50additionalProperties: false
51
52examples:
53  - |
54      interrupt-controller@1f810000 {
55          compatible = "microchip,pic32mzda-evic";
56          reg = <0x1f810000 0x1000>;
57          interrupt-controller;
58          #interrupt-cells = <2>;
59          microchip,external-irqs = <3 8 13 18 23>;
60      };
61