xref: /linux/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml (revision ec2e0fb07d789976c601bec19ecced7a501c3705)
1*01ce6aa5SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*01ce6aa5SRob Herring (Arm)%YAML 1.2
3*01ce6aa5SRob Herring (Arm)---
4*01ce6aa5SRob Herring (Arm)$id: http://devicetree.org/schemas/interrupt-controller/hisilicon,mbigen-v2.yaml#
5*01ce6aa5SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml#
6*01ce6aa5SRob Herring (Arm)
7*01ce6aa5SRob Herring (Arm)title: Hisilicon mbigen v2
8*01ce6aa5SRob Herring (Arm)
9*01ce6aa5SRob Herring (Arm)maintainers:
10*01ce6aa5SRob Herring (Arm)  - Wei Xu <xuwei5@hisilicon.com>
11*01ce6aa5SRob Herring (Arm)
12*01ce6aa5SRob Herring (Arm)description: >
13*01ce6aa5SRob Herring (Arm)  Mbigen means: message based interrupt generator.
14*01ce6aa5SRob Herring (Arm)
15*01ce6aa5SRob Herring (Arm)  MBI is kind of msi interrupt only used on Non-PCI devices.
16*01ce6aa5SRob Herring (Arm)
17*01ce6aa5SRob Herring (Arm)  To reduce the wired interrupt number connected to GIC, Hisilicon designed
18*01ce6aa5SRob Herring (Arm)  mbigen to collect and generate interrupt.
19*01ce6aa5SRob Herring (Arm)
20*01ce6aa5SRob Herring (Arm)  Non-pci devices can connect to mbigen and generate the interrupt by writing
21*01ce6aa5SRob Herring (Arm)  ITS register.
22*01ce6aa5SRob Herring (Arm)
23*01ce6aa5SRob Herring (Arm)properties:
24*01ce6aa5SRob Herring (Arm)  compatible:
25*01ce6aa5SRob Herring (Arm)    const: hisilicon,mbigen-v2
26*01ce6aa5SRob Herring (Arm)
27*01ce6aa5SRob Herring (Arm)  reg:
28*01ce6aa5SRob Herring (Arm)    maxItems: 1
29*01ce6aa5SRob Herring (Arm)
30*01ce6aa5SRob Herring (Arm)required:
31*01ce6aa5SRob Herring (Arm)  - compatible
32*01ce6aa5SRob Herring (Arm)  - reg
33*01ce6aa5SRob Herring (Arm)
34*01ce6aa5SRob Herring (Arm)additionalProperties:
35*01ce6aa5SRob Herring (Arm)  type: object
36*01ce6aa5SRob Herring (Arm)  additionalProperties: false
37*01ce6aa5SRob Herring (Arm)
38*01ce6aa5SRob Herring (Arm)  properties:
39*01ce6aa5SRob Herring (Arm)    interrupt-controller: true
40*01ce6aa5SRob Herring (Arm)
41*01ce6aa5SRob Herring (Arm)    '#interrupt-cells':
42*01ce6aa5SRob Herring (Arm)      const: 2
43*01ce6aa5SRob Herring (Arm)
44*01ce6aa5SRob Herring (Arm)    msi-parent:
45*01ce6aa5SRob Herring (Arm)      maxItems: 1
46*01ce6aa5SRob Herring (Arm)
47*01ce6aa5SRob Herring (Arm)    num-pins:
48*01ce6aa5SRob Herring (Arm)      description: The total number of pins implemented in this Mbigen instance.
49*01ce6aa5SRob Herring (Arm)      $ref: /schemas/types.yaml#/definitions/uint32
50*01ce6aa5SRob Herring (Arm)
51*01ce6aa5SRob Herring (Arm)  required:
52*01ce6aa5SRob Herring (Arm)    - interrupt-controller
53*01ce6aa5SRob Herring (Arm)    - "#interrupt-cells"
54*01ce6aa5SRob Herring (Arm)    - msi-parent
55*01ce6aa5SRob Herring (Arm)    - num-pins
56*01ce6aa5SRob Herring (Arm)
57*01ce6aa5SRob Herring (Arm)examples:
58*01ce6aa5SRob Herring (Arm)  - |
59*01ce6aa5SRob Herring (Arm)    mbigen@c0080000 {
60*01ce6aa5SRob Herring (Arm)        compatible = "hisilicon,mbigen-v2";
61*01ce6aa5SRob Herring (Arm)        reg = <0xc0080000 0x10000>;
62*01ce6aa5SRob Herring (Arm)
63*01ce6aa5SRob Herring (Arm)        mbigen_gmac: intc_gmac {
64*01ce6aa5SRob Herring (Arm)            interrupt-controller;
65*01ce6aa5SRob Herring (Arm)            #interrupt-cells = <2>;
66*01ce6aa5SRob Herring (Arm)            msi-parent = <&its_dsa 0x40b1c>;
67*01ce6aa5SRob Herring (Arm)            num-pins = <9>;
68*01ce6aa5SRob Herring (Arm)        };
69*01ce6aa5SRob Herring (Arm)
70*01ce6aa5SRob Herring (Arm)        mbigen_i2c: intc_i2c {
71*01ce6aa5SRob Herring (Arm)            interrupt-controller;
72*01ce6aa5SRob Herring (Arm)            #interrupt-cells = <2>;
73*01ce6aa5SRob Herring (Arm)            msi-parent = <&its_dsa 0x40b0e>;
74*01ce6aa5SRob Herring (Arm)            num-pins = <2>;
75*01ce6aa5SRob Herring (Arm)        };
76*01ce6aa5SRob Herring (Arm)    };
77