1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX8qxp Display Controller interrupt controller 8 9description: | 10 The Display Controller has a built-in interrupt controller with the following 11 features for all relevant HW events: 12 13 * Enable bit (mask) 14 * Status bit (set by an HW event) 15 * Preset bit (can be used by SW to set status) 16 * Clear bit (used by SW to reset the status) 17 18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable). 19 Alternatively the un-masked trigger signals for all HW events are provided, 20 allowing it to use a global interrupt controller instead. 21 22 Each interrupt can be protected against SW running in user mode. In that case, 23 only privileged AHB access can control the interrupt status. 24 25maintainers: 26 - Liu Ying <victor.liu@nxp.com> 27 28properties: 29 compatible: 30 const: fsl,imx8qxp-dc-intc 31 32 reg: 33 maxItems: 1 34 35 clocks: 36 maxItems: 1 37 38 interrupt-controller: true 39 40 "#interrupt-cells": 41 const: 1 42 43 interrupts: 44 items: 45 - description: store9 shadow load interrupt(blit engine) 46 - description: store9 frame complete interrupt(blit engine) 47 - description: store9 sequence complete interrupt(blit engine) 48 - description: 49 extdst0 shadow load interrupt 50 (display controller, content stream 0) 51 - description: 52 extdst0 frame complete interrupt 53 (display controller, content stream 0) 54 - description: 55 extdst0 sequence complete interrupt 56 (display controller, content stream 0) 57 - description: 58 extdst4 shadow load interrupt 59 (display controller, safety stream 0) 60 - description: 61 extdst4 frame complete interrupt 62 (display controller, safety stream 0) 63 - description: 64 extdst4 sequence complete interrupt 65 (display controller, safety stream 0) 66 - description: 67 extdst1 shadow load interrupt 68 (display controller, content stream 1) 69 - description: 70 extdst1 frame complete interrupt 71 (display controller, content stream 1) 72 - description: 73 extdst1 sequence complete interrupt 74 (display controller, content stream 1) 75 - description: 76 extdst5 shadow load interrupt 77 (display controller, safety stream 1) 78 - description: 79 extdst5 frame complete interrupt 80 (display controller, safety stream 1) 81 - description: 82 extdst5 sequence complete interrupt 83 (display controller, safety stream 1) 84 - description: 85 disengcfg0 shadow load interrupt 86 (display controller, display stream 0) 87 - description: 88 disengcfg0 frame complete interrupt 89 (display controller, display stream 0) 90 - description: 91 disengcfg0 sequence complete interrupt 92 (display controller, display stream 0) 93 - description: 94 framegen0 programmable interrupt0 95 (display controller, display stream 0) 96 - description: 97 framegen0 programmable interrupt1 98 (display controller, display stream 0) 99 - description: 100 framegen0 programmable interrupt2 101 (display controller, display stream 0) 102 - description: 103 framegen0 programmable interrupt3 104 (display controller, display stream 0) 105 - description: 106 signature0 shadow load interrupt 107 (display controller, display stream 0) 108 - description: 109 signature0 measurement valid interrupt 110 (display controller, display stream 0) 111 - description: 112 signature0 error condition interrupt 113 (display controller, display stream 0) 114 - description: 115 disengcfg1 shadow load interrupt 116 (display controller, display stream 1) 117 - description: 118 disengcfg1 frame complete interrupt 119 (display controller, display stream 1) 120 - description: 121 disengcfg1 sequence complete interrupt 122 (display controller, display stream 1) 123 - description: 124 framegen1 programmable interrupt0 125 (display controller, display stream 1) 126 - description: 127 framegen1 programmable interrupt1 128 (display controller, display stream 1) 129 - description: 130 framegen1 programmable interrupt2 131 (display controller, display stream 1) 132 - description: 133 framegen1 programmable interrupt3 134 (display controller, display stream 1) 135 - description: 136 signature1 shadow load interrupt 137 (display controller, display stream 1) 138 - description: 139 signature1 measurement valid interrupt 140 (display controller, display stream 1) 141 - description: 142 signature1 error condition interrupt 143 (display controller, display stream 1) 144 - description: reserved 145 - description: 146 command sequencer error condition interrupt(command sequencer) 147 - description: 148 common control software interrupt0(common control) 149 - description: 150 common control software interrupt1(common control) 151 - description: 152 common control software interrupt2(common control) 153 - description: 154 common control software interrupt3(common control) 155 - description: 156 framegen0 synchronization status activated interrupt 157 (display controller, safety stream 0) 158 - description: 159 framegen0 synchronization status deactivated interrupt 160 (display controller, safety stream 0) 161 - description: 162 framegen0 synchronization status activated interrupt 163 (display controller, content stream 0) 164 - description: 165 framegen0 synchronization status deactivated interrupt 166 (display controller, content stream 0) 167 - description: 168 framegen1 synchronization status activated interrupt 169 (display controller, safety stream 1) 170 - description: 171 framegen1 synchronization status deactivated interrupt 172 (display controller, safety stream 1) 173 - description: 174 framegen1 synchronization status activated interrupt 175 (display controller, content stream 1) 176 - description: 177 framegen1 synchronization status deactivated interrupt 178 (display controller, content stream 1) 179 minItems: 49 180 181 interrupt-names: 182 items: 183 - const: store9_shdload 184 - const: store9_framecomplete 185 - const: store9_seqcomplete 186 - const: extdst0_shdload 187 - const: extdst0_framecomplete 188 - const: extdst0_seqcomplete 189 - const: extdst4_shdload 190 - const: extdst4_framecomplete 191 - const: extdst4_seqcomplete 192 - const: extdst1_shdload 193 - const: extdst1_framecomplete 194 - const: extdst1_seqcomplete 195 - const: extdst5_shdload 196 - const: extdst5_framecomplete 197 - const: extdst5_seqcomplete 198 - const: disengcfg_shdload0 199 - const: disengcfg_framecomplete0 200 - const: disengcfg_seqcomplete0 201 - const: framegen0_int0 202 - const: framegen0_int1 203 - const: framegen0_int2 204 - const: framegen0_int3 205 - const: sig0_shdload 206 - const: sig0_valid 207 - const: sig0_error 208 - const: disengcfg_shdload1 209 - const: disengcfg_framecomplete1 210 - const: disengcfg_seqcomplete1 211 - const: framegen1_int0 212 - const: framegen1_int1 213 - const: framegen1_int2 214 - const: framegen1_int3 215 - const: sig1_shdload 216 - const: sig1_valid 217 - const: sig1_error 218 - const: reserved 219 - const: cmdseq_error 220 - const: comctrl_sw0 221 - const: comctrl_sw1 222 - const: comctrl_sw2 223 - const: comctrl_sw3 224 - const: framegen0_primsync_on 225 - const: framegen0_primsync_off 226 - const: framegen0_secsync_on 227 - const: framegen0_secsync_off 228 - const: framegen1_primsync_on 229 - const: framegen1_primsync_off 230 - const: framegen1_secsync_on 231 - const: framegen1_secsync_off 232 minItems: 49 233 234required: 235 - compatible 236 - reg 237 - clocks 238 - interrupt-controller 239 - "#interrupt-cells" 240 - interrupts 241 - interrupt-names 242 243additionalProperties: false 244 245examples: 246 - | 247 #include <dt-bindings/clock/imx8-lpcg.h> 248 249 interrupt-controller@56180040 { 250 compatible = "fsl,imx8qxp-dc-intc"; 251 reg = <0x56180040 0x60>; 252 clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; 253 interrupt-controller; 254 interrupt-parent = <&dc0_irqsteer>; 255 #interrupt-cells = <1>; 256 interrupts = <448>, <449>, <450>, <64>, 257 <65>, <66>, <67>, <68>, 258 <69>, <70>, <193>, <194>, 259 <195>, <196>, <197>, <72>, 260 <73>, <74>, <75>, <76>, 261 <77>, <78>, <79>, <80>, 262 <81>, <199>, <200>, <201>, 263 <202>, <203>, <204>, <205>, 264 <206>, <207>, <208>, <5>, 265 <0>, <1>, <2>, <3>, 266 <4>, <82>, <83>, <84>, 267 <85>, <209>, <210>, <211>, 268 <212>; 269 interrupt-names = "store9_shdload", 270 "store9_framecomplete", 271 "store9_seqcomplete", 272 "extdst0_shdload", 273 "extdst0_framecomplete", 274 "extdst0_seqcomplete", 275 "extdst4_shdload", 276 "extdst4_framecomplete", 277 "extdst4_seqcomplete", 278 "extdst1_shdload", 279 "extdst1_framecomplete", 280 "extdst1_seqcomplete", 281 "extdst5_shdload", 282 "extdst5_framecomplete", 283 "extdst5_seqcomplete", 284 "disengcfg_shdload0", 285 "disengcfg_framecomplete0", 286 "disengcfg_seqcomplete0", 287 "framegen0_int0", 288 "framegen0_int1", 289 "framegen0_int2", 290 "framegen0_int3", 291 "sig0_shdload", 292 "sig0_valid", 293 "sig0_error", 294 "disengcfg_shdload1", 295 "disengcfg_framecomplete1", 296 "disengcfg_seqcomplete1", 297 "framegen1_int0", 298 "framegen1_int1", 299 "framegen1_int2", 300 "framegen1_int3", 301 "sig1_shdload", 302 "sig1_valid", 303 "sig1_error", 304 "reserved", 305 "cmdseq_error", 306 "comctrl_sw0", 307 "comctrl_sw1", 308 "comctrl_sw2", 309 "comctrl_sw3", 310 "framegen0_primsync_on", 311 "framegen0_primsync_off", 312 "framegen0_secsync_on", 313 "framegen0_secsync_off", 314 "framegen1_primsync_on", 315 "framegen1_primsync_off", 316 "framegen1_secsync_on", 317 "framegen1_secsync_off"; 318 }; 319