xref: /linux/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml (revision 6e9a12f85a7567bb9a41d5230468886bd6a27b20) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Nested Vector Interrupt Controller (NVIC)
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description:
13  The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
14  based processor cores.  The NVIC implemented on different SoCs vary in the
15  number of interrupts and priority bits per interrupt.
16
17properties:
18  compatible:
19    enum:
20      - arm,armv7m-nvic # deprecated
21      - arm,v6m-nvic
22      - arm,v7m-nvic
23      - arm,v8m-nvic
24
25  reg:
26    maxItems: 1
27
28  '#address-cells':
29    const: 0
30
31  interrupt-controller: true
32
33  '#interrupt-cells':
34    enum: [1, 2]
35    description: |
36      Number of cells to encode an interrupt source:
37      first = interrupt number, second = priority.
38
39  arm,num-irq-priority-bits:
40    description: Number of priority bits implemented by the SoC
41    minimum: 1
42    maximum: 8
43
44required:
45  - compatible
46  - reg
47  - interrupt-controller
48  - '#interrupt-cells'
49  - arm,num-irq-priority-bits
50
51additionalProperties: false
52
53examples:
54  - |
55    interrupt-controller@e000e100 {
56        compatible = "arm,v7m-nvic";
57        #interrupt-cells = <2>;
58        #address-cells = <0>;
59        interrupt-controller;
60        reg = <0xe000e100 0xc00>;
61        arm,num-irq-priority-bits = <4>;
62    };
63