1*930222f3SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*930222f3SRob Herring (Arm)%YAML 1.2 3*930222f3SRob Herring (Arm)--- 4*930222f3SRob Herring (Arm)$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# 5*930222f3SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*930222f3SRob Herring (Arm) 7*930222f3SRob Herring (Arm)title: ARM Nested Vector Interrupt Controller (NVIC) 8*930222f3SRob Herring (Arm) 9*930222f3SRob Herring (Arm)maintainers: 10*930222f3SRob Herring (Arm) - Rob Herring <robh@kernel.org> 11*930222f3SRob Herring (Arm) 12*930222f3SRob Herring (Arm)description: 13*930222f3SRob Herring (Arm) The NVIC provides an interrupt controller that is tightly coupled to Cortex-M 14*930222f3SRob Herring (Arm) based processor cores. The NVIC implemented on different SoCs vary in the 15*930222f3SRob Herring (Arm) number of interrupts and priority bits per interrupt. 16*930222f3SRob Herring (Arm) 17*930222f3SRob Herring (Arm)properties: 18*930222f3SRob Herring (Arm) compatible: 19*930222f3SRob Herring (Arm) enum: 20*930222f3SRob Herring (Arm) - arm,v6m-nvic 21*930222f3SRob Herring (Arm) - arm,v7m-nvic 22*930222f3SRob Herring (Arm) - arm,v8m-nvic 23*930222f3SRob Herring (Arm) 24*930222f3SRob Herring (Arm) reg: 25*930222f3SRob Herring (Arm) maxItems: 1 26*930222f3SRob Herring (Arm) 27*930222f3SRob Herring (Arm) '#address-cells': 28*930222f3SRob Herring (Arm) const: 0 29*930222f3SRob Herring (Arm) 30*930222f3SRob Herring (Arm) interrupt-controller: true 31*930222f3SRob Herring (Arm) 32*930222f3SRob Herring (Arm) '#interrupt-cells': 33*930222f3SRob Herring (Arm) const: 2 34*930222f3SRob Herring (Arm) description: | 35*930222f3SRob Herring (Arm) Number of cells to encode an interrupt source: 36*930222f3SRob Herring (Arm) first = interrupt number, second = priority. 37*930222f3SRob Herring (Arm) 38*930222f3SRob Herring (Arm) arm,num-irq-priority-bits: 39*930222f3SRob Herring (Arm) description: Number of priority bits implemented by the SoC 40*930222f3SRob Herring (Arm) minimum: 1 41*930222f3SRob Herring (Arm) maximum: 8 42*930222f3SRob Herring (Arm) 43*930222f3SRob Herring (Arm)required: 44*930222f3SRob Herring (Arm) - compatible 45*930222f3SRob Herring (Arm) - reg 46*930222f3SRob Herring (Arm) - interrupt-controller 47*930222f3SRob Herring (Arm) - '#interrupt-cells' 48*930222f3SRob Herring (Arm) - arm,num-irq-priority-bits 49*930222f3SRob Herring (Arm) 50*930222f3SRob Herring (Arm)additionalProperties: false 51*930222f3SRob Herring (Arm) 52*930222f3SRob Herring (Arm)examples: 53*930222f3SRob Herring (Arm) - | 54*930222f3SRob Herring (Arm) interrupt-controller@e000e100 { 55*930222f3SRob Herring (Arm) compatible = "arm,v7m-nvic"; 56*930222f3SRob Herring (Arm) #interrupt-cells = <2>; 57*930222f3SRob Herring (Arm) #address-cells = <0>; 58*930222f3SRob Herring (Arm) interrupt-controller; 59*930222f3SRob Herring (Arm) reg = <0xe000e100 0xc00>; 60*930222f3SRob Herring (Arm) arm,num-irq-priority-bits = <4>; 61*930222f3SRob Herring (Arm) }; 62