1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iio/frequency/adi,adf41513.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Analog Devices ADF41513 PLL Frequency Synthesizer 8 9maintainers: 10 - Rodrigo Alencar <rodrigo.alencar@analog.com> 11 12description: 13 The ADF41513 is an ultralow noise frequency synthesizer that can be used to 14 implement local oscillators (LOs) as high as 26.5 GHz in the upconversion and 15 downconversion sections of wireless receivers and transmitters. The ADF41510 16 supports frequencies up to 10 GHz. 17 18 https://www.analog.com/en/products/adf41510.html 19 https://www.analog.com/en/products/adf41513.html 20 21properties: 22 compatible: 23 enum: 24 - adi,adf41510 25 - adi,adf41513 26 27 reg: 28 maxItems: 1 29 30 spi-max-frequency: 31 maximum: 25000000 32 33 clocks: 34 maxItems: 1 35 description: Clock that provides the reference input frequency. 36 37 avdd1-supply: 38 description: PFD and Up and Down Digital Driver Power Supply (3.3 V) 39 40 avdd2-supply: 41 description: RF Buffer and Prescaler Power Supply (3.3 V) 42 43 avdd3-supply: 44 description: N Divider Power Supply (3.3 V) 45 46 avdd4-supply: 47 description: R Divider and Lock Detector Power Supply (3.3 V) 48 49 avdd5-supply: 50 description: Sigma-Delta Modulator and SPI Power Supply (3.3 V) 51 52 vp-supply: 53 description: Charge Pump Power Supply (3.3 V) 54 55 enable-gpios: 56 description: 57 GPIO that controls the chip enable pin. A logic low on this pin 58 powers down the device and puts the charge pump output into 59 three-state mode. 60 maxItems: 1 61 62 lock-detect-gpios: 63 description: 64 GPIO for lock detect functionality. When configured for digital lock 65 detect, this pin will output a logic high when the PLL is locked. 66 maxItems: 1 67 68 adi,power-up-frequency-mhz: 69 minimum: 1000 70 maximum: 26500 71 default: 10000 72 description: 73 The PLL tunes to this frequency during the initialization sequence. 74 This property should be set to a frequency supported by the loop filter 75 and VCO used in the design. Range is 1 GHz to 26.5 GHz for ADF41513, 76 and 1 GHz to 10 GHz for ADF41510. 77 78 adi,reference-div-factor: 79 $ref: /schemas/types.yaml#/definitions/uint32 80 minimum: 1 81 maximum: 32 82 default: 1 83 description: 84 Value for the reference division factor (R Counter). The driver will 85 increment R Counter as needed to achieve a PFD frequency within the 86 allowed range. High R counter values will reduce the PFD frequency, which 87 lowers the frequency resolution, and affects phase noise performance. 88 As it affects the PFD frequency, this value depends on the loop filter 89 design. 90 91 adi,reference-doubler-enable: 92 description: 93 Enables the reference doubler when deriving the PFD frequency. 94 The maximum reference frequency when the doubler is enabled is 225 MHz. 95 As it affects the PFD frequency, this value depends on the loop filter 96 design. 97 type: boolean 98 99 adi,reference-div2-enable: 100 description: 101 Enables the reference divide-by-2 function when deriving the PFD 102 frequency. As it affects the PFD frequency, this value depends on the 103 loop filter design. 104 type: boolean 105 106 adi,charge-pump-resistor-ohms: 107 minimum: 1800 108 maximum: 10000 109 default: 2700 110 description: 111 External charge pump resistor (R_SET) value in ohms. This sets the maximum 112 charge pump current along with the charge pump current setting. 113 114 adi,charge-pump-current-microamp: 115 minimum: 81 116 maximum: 7200 117 description: 118 Charge pump current (I_CP) in microamps. The value will be rounded to the 119 nearest supported value. Range of acceptable values depends on the 120 charge pump resistor value, such that 810 mV <= I_CP * R_SET <= 12960 mV. 121 This value depends on the loop filter and the VCO design. 122 123 adi,logic-level-1v8-enable: 124 description: 125 Set MUXOUT and DLD logic levels to 1.8V. Default is 3.3V. 126 type: boolean 127 128 adi,phase-detector-polarity-positive-enable: 129 description: 130 Set phase detector polarity to positive. Default is negative. 131 Use positive polarity with non-inverting loop filter and VCO with 132 positive tuning slope, or with inverting loop filter and VCO with 133 negative tuning slope. 134 type: boolean 135 136 adi,lock-detector-count: 137 $ref: /schemas/types.yaml#/definitions/uint32 138 default: 64 139 description: 140 Sets the value for Lock Detector count of the PLL, which determines the 141 number of consecutive phase detector cycles that must be within the lock 142 detector window before lock is declared. Lower values increase the lock 143 detection sensitivity, while higher values provides a more stable lock 144 detection. Applications that consume the lock detect signal may require 145 different settings based on system requirements. 146 enum: [2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192] 147 148 adi,phase-resync-period-ns: 149 default: 0 150 description: 151 When this value is non-zero, enable phase resync functionality, which 152 produces a consistent output phase offset with respect to the input 153 reference. The value specifies the resync period in nanoseconds, used 154 to configure clock dividers with respect to the PFD frequency. This value 155 should be set to a value that is at least as long as the worst case lock 156 time, i.e., it depends mostly on the loop filter design. 157 158 adi,le-sync-enable: 159 description: 160 Synchronizes Load Enable (LE) transitions with the reference signal to 161 avoid asynchronous glitches in the output. This is recommended when using 162 the PLL as a frequency synthesizer, where the reference signal will always 163 be present while the device is being configured. When using the PLL as a 164 frequency tracker, where the reference signal may be absent, LE sync 165 should be left disabled. 166 type: boolean 167 168dependencies: 169 adi,charge-pump-resistor-ohms: [ 'adi,charge-pump-current-microamp' ] 170 171required: 172 - compatible 173 - reg 174 - clocks 175 - avdd1-supply 176 - avdd2-supply 177 - avdd3-supply 178 - avdd4-supply 179 - avdd5-supply 180 - vp-supply 181 182allOf: 183 - $ref: /schemas/spi/spi-peripheral-props.yaml# 184 - if: 185 properties: 186 compatible: 187 contains: 188 const: adi,adf41510 189 then: 190 properties: 191 adi,power-up-frequency-mhz: 192 maximum: 10000 193 194unevaluatedProperties: false 195 196examples: 197 - | 198 #include <dt-bindings/gpio/gpio.h> 199 spi { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 pll@0 { 204 compatible = "adi,adf41513"; 205 reg = <0>; 206 spi-max-frequency = <25000000>; 207 clocks = <&ref_clk>; 208 avdd1-supply = <&avdd1_3v3>; 209 avdd2-supply = <&avdd2_3v3>; 210 avdd3-supply = <&avdd3_3v3>; 211 avdd4-supply = <&avdd4_3v3>; 212 avdd5-supply = <&avdd5_3v3>; 213 vp-supply = <&vp_3v3>; 214 enable-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; 215 lock-detect-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; 216 217 adi,power-up-frequency-mhz = <15500>; 218 adi,charge-pump-current-microamp = <3600>; 219 adi,charge-pump-resistor-ohms = <2700>; 220 adi,reference-doubler-enable; 221 adi,lock-detector-count = <64>; 222 adi,phase-resync-period-ns = <0>; 223 adi,phase-detector-polarity-positive-enable; 224 adi,le-sync-enable; 225 }; 226 }; 227... 228